Assigning Confidence to Conditional Branch Predictions. - Erik Jacobsen; Eric Rotenberg; James E. Smith 001 (MICRO, 1996)

Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. - Eric Rotenberg; Steve Bennett; James E. Smith 001 (MICRO, 1996)

Path-Based Next Trace Prediction. - Quinn Jacobson; Eric Rotenberg; James E. Smith 001 (MICRO, 1997)

Trace Processors. - Eric Rotenberg; Quinn Jacobson; Yiannakis Sazeides; James E. Smith 001 (MICRO, 1997)

AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. - Eric Rotenberg (FTCS, 1999)

A Study of Control Independence in Superscalar Processors. - Eric Rotenberg; Quinn Jacobson; James E. Smith 001 (HPCA, 1999)

A Trace Cache Microarchitecture and Evaluation. - Eric Rotenberg; Steve Bennett; James E. Smith 001 (IEEE Trans. Computers, 1999)

Slipstream Processors: Improving both Performance and Fault Tolerance. - Karthik Sundaramoorthy; Zachary Purser; Eric Rotenberg (ASPLOS, 2000)

A study of slipstream processors. - Zachary Purser; Karthik Sundaramoorthy; Eric Rotenberg (MICRO, 2000)

Control Independence in Trace Processors. - Eric Rotenberg; James E. Smith 001 (J. Instr. Level Parallelism, 2000)

Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems. - Eric Rotenberg (MICRO, 2001)

A case for dynamic pipeline scaling. - Jinson Koppanalil; Prakash Ramrakhyani; Sameer Desai; Anu Vaidyanathan; Eric Rotenberg (CASES, 2002)

A Large, Fast Instruction Window for Tolerating Cache Misses. - Alvin R. Lebeck; Tong Li 003; Eric Rotenberg; Jinson Koppanalil; Jaidev P. Patwardhan (ISCA, 2002)

Slipstream Execution Mode for CMP-Based Multiprocessors. - Khaled Z. Ibrahim; Gregory T. Byrd; Eric Rotenberg (HPCA, 2003)

Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems. - Aravindh Anantaraman; Kiran Seth; Kaustubh Patil; Eric Rotenberg; Frank Mueller 001 (ISCA, 2003)

Adaptive mode control: A static-power-efficient cache design. - Huiyang Zhou; Mark C. Toburen; Eric Rotenberg; Thomas M. Conte (ACM Trans. Embed. Comput. Syst., 2003)

Safely exploiting multithreaded processors to tolerate memory latency in real-time systems. - Ali El-Haj-Mahmoud; Eric Rotenberg (CASES, 2004)

Enforcing Safety of Real-Time Schedules on Contemporary Processors Using a Virtual Simple Architecture (VISA). - Aravindh Anantaraman; Kiran Seth; Eric Rotenberg; Frank Mueller 001 (RTSS, 2004)

A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors. - Jinson Koppanalil; Eric Rotenberg (IEEE Trans. Computers, 2004)

Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing. - Ali El-Haj-Mahmoud; Ahmed S. Al-Zawawi; Aravindh Anantaraman; Eric Rotenberg (CASES, 2005)

Tapping ZettaRAMTM for Low-Power Memory Systems. - Ravi K. Venkatesan; Ahmed S. Al-Zawawi; Eric Rotenberg (HPCA, 2005)

Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance. - Vimal K. Reddy; Eric Rotenberg; Sailashri Parthasarathy (ASPLOS, 2006)

Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM. - Ravi K. Venkatesan; Stephen Herr; Eric Rotenberg (HPCA, 2006)

Assertion-Based Microarchitecture Design for Improved Reliability. - Vimal K. Reddy; Eric Rotenberg; Ahmed S. Al-Zawawi (ICCD, 2006)

The State of ZettaRAM. - Eric Rotenberg; Ravi V. Venkatesan (Nano-Net, 2006)

Non-uniform program analysis & repeatable execution constraints: exploiting out-of-order processors in real-time systems. - Aravindh Anantaraman; Eric Rotenberg (SIGBED Rev., 2006)

FAST: Frequency-aware static timing analysis. - Kiran Seth; Aravindh Anantaraman; Frank Mueller 001; Eric Rotenberg (ACM Trans. Embed. Comput. Syst., 2006)

Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance. - Vimal K. Reddy; Eric Rotenberg (DSN, 2007)

Transparent control independence (TCI). - Ahmed S. Al-Zawawi; Vimal K. Reddy; Eric Rotenberg; Haitham Akkary (ISCA, 2007)

Architectural contesting: exposing and exploiting temperamental behavior. - Hashem Hashemi Najaf-abadi; Eric Rotenberg (SIGARCH Comput. Archit. News, 2007)

ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling. - Ravi K. Venkatesan; Ahmed S. Al-Zawawi; Krishnan Sivasubramanian; Eric Rotenberg (IEEE Trans. Computers, 2007)

Coverage of a microarchitecture-level fault check regimen in a superscalar processor. - Vimal K. Reddy; Eric Rotenberg (DSN, 2008)

Configurational Workload Characterization. - Hashem Hashemi Najaf-abadi; Eric Rotenberg (ISPASS, 2008)

Core-Selectability in Chip Multiprocessors. - Hashem Hashemi Najaf-abadi; Niket Kumar Choudhary; Eric Rotenberg (PACT, 2009)

Architectural Contesting. - Hashem Hashemi Najaf-abadi; Eric Rotenberg (HPCA, 2009)

The importance of accurate task arrival characterization in the design of processing cores. - Hashem Hashemi Najaf-abadi; Eric Rotenberg (IISWC, 2009)

Criticality-driven superscalar design space exploration. - Sandeep Navada; Niket Kumar Choudhary; Eric Rotenberg (PACT, 2010)

EXACT: explicit dynamic-branch prediction with active updates. - Muawya Al-Otoom; Elliott Forbes; Eric Rotenberg (Conf. Computing Frontiers, 2010)

FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template. - Niket Kumar Choudhary; Salil V. Wadhavkar; Tanmay A. Shah; Hiran Mayukh; Jayneel Gandhi; Brandon H. Dwiel; Sandeep Navada; Hashem Hashemi Najaf-abadi; Eric Rotenberg (ISCA, 2011)

FPGA modeling of diverse superscalar processors. - Brandon H. Dwiel; Niket Kumar Choudhary; Eric Rotenberg (ISPASS, 2012)

Control-Flow Decoupling. - Rami Sheikh; James Tuck 001; Eric Rotenberg (MICRO, 2012)

A physical design study of fabscalar-generated superscalar cores. - Niket K. Choudhary; Brandon H. Dwiel; Eric Rotenberg (VLSI-SoC, 2012)

FabScalar: Automating Superscalar Core Design. - Niket Kumar Choudhary; Salil V. Wadhavkar; Tanmay A. Shah; Hiran Mayukh; Jayneel Gandhi; Brandon H. Dwiel; Sandeep Navada; Hashem Hashemi Najaf-abadi; Eric Rotenberg (IEEE Micro, 2012)

Design of controller for L2 cache mapped in Tezzaron stacked DRAM. - Nyunyi M. Tshibangu; Paul D. Franzon; Eric Rotenberg; William Rhett Davis (3DIC, 2013)

A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors. - Sandeep Navada; Niket K. Choudhary; Salil V. Wadhavkar; Eric Rotenberg (PACT, 2013)

Rationale for a 3D heterogeneous multi-core processor. - Eric Rotenberg; Brandon H. Dwiel; Elliott Forbes; Zhenqian Zhang; Randy Widialaksono; Rangeen Basu Roy Chowdhury; Nyunyi M. Tshibangu; Steve Lipa; W. Rhett Davis; Paul D. Franzon (ICCD, 2013)

Hetero2 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors. - Shivam Priyadarshi; Niket K. Choudhary; Brandon H. Dwiel; Ankita Upreti; Eric Rotenberg; William Rhett Davis; Paul D. Franzon (ISQED, 2013)

3D-enabled customizable embedded computer (3DECC). - Paul D. Franzon; Eric Rotenberg; James Tuck 001; Huiyang Zhou; W. Rhett Davis; Hongwen Dai; Joonmoo Huh; Sungkwan Ku; Steve Lipa; Chao Li 004; Jong Beom Park; Joshua Schabel (3DIC, 2014)

Co-simulation framework for streamlining microprocessor development on standard ASIC design flow. - Tomoyuki Nakabayashi; Tomoyuki Sugiyama; Takahiro Sasaki; Eric Rotenberg; Toshio Kondo (ASP-DAC, 2014)

Design-effort alloy: Boosting a highly tuned primary core with untuned alternate cores. - Elliott Forbes; Niket Kumar Choudhary; Brandon H. Dwiel; Eric Rotenberg (ICCD, 2014)

Computing in 3D. - Paul D. Franzon; Eric Rotenberg; James Tuck 001; W. Rhett Davis; Huiyang Zhou; Joshua Schabel; Zhenqian Zhang; J. Brandon Dwiel; Elliott Forbes; Joonmoo Huh; Marcus Tshibangu; Steve Lipa (3DIC, 2015)

Computing in 3D. - Paul D. Franzon; Eric Rotenberg; James Tuck 001; W. Rhett Davis; Huiyang Zhou; Joshua Schabel; Zhenqian Zhang; J. Brandon Dwiel; Elliott Forbes; Joonmoo Huh; Steve Lipa (CICC, 2015)

Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor. - Elliott Forbes; Zhenqian Zhang; Randy Widialaksono; Brandon H. Dwiel; Rangeen Basu Roy Chowdhury; Vinesh Srinivasan; Steve Lipa; Eric Rotenberg; W. Rhett Davis; Paul D. Franzon (Hot Chips Symposium, 2015)

Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching. - Rami Sheikh; James Tuck 001; Eric Rotenberg (IEEE Trans. Computers, 2015)

Physical design of a 3D-stacked heterogeneous multi-core processor. - Randy Widialaksono; Rangeen Basu Roy Chowdhury; Zhenqian Zhang; Joshua Schabel; Steve Lipa; Eric Rotenberg; W. Rhett Davis; Paul D. Franzon (3DIC, 2016)

AnyCore-1: A comprehensively adaptive 4-way superscalar processor. - Rangeen Basu Roy Chowdhury; Anil K. Kannepalli; Eric Rotenberg (Hot Chips Symposium, 2016)

Fast register consolidation and migration for heterogeneous multi-core processors. - Elliott Forbes; Eric Rotenberg (ICCD, 2016)

AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores. - Rangeen Basu Roy Chowdhury; Anil K. Kannepalli; Sungkwan Ku; Eric Rotenberg (ISPASS, 2016)

H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor. - Vinesh Srinivasan; Rangeen Basu Roy Chowdhury; Elliott Forbes; Randy Widialaksono; Zhenqian Zhang; Joshua Schabel; Sungkwan Ku; Steve Lipa; Eric Rotenberg; W. Rhett Davis; Paul D. Franzon (ICCD, 2017)

A case for standard-cell based RAMs in highly-ported superscalar processor structures. - Sungkwan Ku; Elliott Forbes; Rangeen Basu Roy Chowdhury; Eric Rotenberg (ISQED, 2017)

Slipstream Processors Revisited: Exploiting Branch Sets. - Vinesh Srinivasan; Rangeen Basu Roy Chowdhury; Eric Rotenberg (ISCA, 2020)

Post-Silicon Microarchitecture. - Chanchal Kumar; Aayush Chaudhary; Shubham Bhawalkar; Utkarsh Mathur; Saransh Jain; Adith Vastrad; Eric Rotenberg (IEEE Comput. Archit. Lett., 2020)

Post-Fabrication Microarchitecture. - Chanchal Kumar; Anirudh Seshadri; Aayush Chaudhary; Shubham Bhawalkar; Rohit Singh; Eric Rotenberg (MICRO, 2021)

SpecMPK: Efficient In-Process Isolation with Speculative and Secure Permission Update Instruction. - Debpratim Adak; Huiyang Zhou; Eric Rotenberg; Amro Awad (HPCA, 2025)

Delinquent Loop Pre-execution Using Predicated Helper Threads. - Anirudh Seshadri; Eric Rotenberg (HPCA, 2025)