A fully bypassed six-issue integer datapath and register file on the Itanium-2 microprocessor. - Eric S. Fetzer; Mark Gibson; Anthony Klein; Naomi Calick; Chengyu Zhu; Eric Busta; Baker Mohammad (IEEE J. Solid State Circuits, 2002)

Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design. - Eric S. Fetzer (IEEE Des. Test Comput., 2006)

The Parity protected, multithreaded register files on the 90-nm itanium microprocessor. - Eric S. Fetzer; David M. Dahle; Casey Little; Kevin Safford (IEEE J. Solid State Circuits, 2006)

A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers. - Reid J. Riedlinger; Rohit Bhatia; Larry L. Biro; William J. Bowhill; Eric S. Fetzer; Paul E. Gronowski; Tom Grutkowski (ISSCC, 2011)

A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers. - Reid J. Riedlinger; Ron Arnold; Larry L. Biro; William J. Bowhill; Jason Crop; Kevin Duda; Eric S. Fetzer; Olivier Franza; Tom Grutkowski; Casey Little; Charles Morganti; Gary Moyer; et al. (IEEE J. Solid State Circuits, 2012)

New generation carry look twice-ahead adder CL2A and carry look thrice-ahead adder CL3A. - Lalitha Mohana Kalyani-Garimella; Sri Raga Sudha Garimella; Kevin Duda; Eric S. Fetzer (MWSCAS, 2013)