A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digital conversion of a 10 MHz FM signal. - Ian Galton; William Huff; Paolo Carbone; Eric Siragusa (IEEE J. Solid State Circuits, 1998)

Segmented mismatch-shaping D/A conversion. - Asaf Fishov; Eric Siragusa; Jared Welz; Eric Fogleman; Ian Galton (ISCAS (4), 2002)

A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC. - Eric Siragusa; Ian Galton (IEEE J. Solid State Circuits, 2004)

A 16b 80MS/s 100mW 77.6dB SNR CMOS pipeline ADC. - Janet Brunsilius; Eric Siragusa; Steve Kosic; Frank Murden; Ege Yetis; Binh Luu; Jeff Bray; Phil Brown; Allen Barlow (ISSCC, 2011)