Facilitating superscalar processing via a combined static/dynamic register renaming scheme. - Eric Sprangle; Yale N. Patt (MICRO, 1994)

The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference. - Eric Sprangle; Robert S. Chappell; Mitch Alsup; Yale N. Patt (ISCA, 1997)

Increasing Processor Performance by Implementing Deeper Pipelines. - Eric Sprangle; Doug Carmean (ISCA, 2002)

Enabling scalability and performance in a large scale CMP environment. - Bratin Saha; Ali-Reza Adl-Tabatabai; Anwar M. Ghuloum; Mohan Rajagopalan; Richard L. Hudson; Leaf Petersen; Vijay Menon 002; Brian R. Murphy; Tatiana Shpeisman; Eric Sprangle; Anwar Rohillah; Doug Carmean; et al. (EuroSys, 2007)

Larrabee: A Many-Core x86 Architecture for Visual Computing. - Larry Seiler; Doug Carmean; Eric Sprangle; Tom Forsyth; Pradeep Dubey; Stephen Junkins; Adam T. Lake; Robert Cavin; Roger Espasa; Ed Grochowski; Toni Juan; Michael Abrash; et al. (IEEE Micro, 2009)