VLSI design of densely-connected array processors. - Eric Y. Chou; Bing J. Sheu; Tony H. Wu; Robert C. Chang (ICCD, 1995)

A compact VLSI design for recursive neural networks with hardware annealing capability. - Eric Y. Chou; Bing J. Sheu; Steve H. Jen (ICNN, 1995)

A hippocampal model implementation using VLSI table-look-up and model-based approaches. - Richard H. Tsai; Eric Y. Chou; Bing J. Sheu; Theodore W. Berger (ICNN, 1995)

A neural network communication equalizer with optimized solution capability. - David C. Chen 001; Bing J. Sheu; Eric Y. Chou (ICNN, 1996)

Low power salient integration mode image sensor with a low voltage mixed-signal readout architecture. - Eric Y. Chou; A. J. Budrys; Kit M. Cham (ISLPED, 1998)