Reducing bit flipping problems in SRAM physical unclonable functions for chip identification. - Susana Eiroa; Javier Castro-Ramirez; Macarena Cristina Martínez-Rodríguez; Erica Tena; Piedad Brox; Iluminada Baturone (ICECS, 2012)

ASIC-in-the-loop methodology for verification of piecewise affine controllers. - Macarena C. Martínez-Rodríguez; Piedad Brox; Javier Castro-Ramirez; Erica Tena; Antonio J. Acosta 001; Iluminada Baturone (ICECS, 2012)

A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions. - Piedad Brox; Javier Castro-Ramirez; Macarena C. Martínez-Rodríguez; Erica Tena; Carlos Jesús Jiménez-Fernández; Iluminada Baturone; Antonio J. Acosta 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Low-Power Differential Logic Gates for DPA Resistant Circuits. - Erica Tena-Sánchez; Javier Castro-Ramirez; Antonio J. Acosta 001 (DSD, 2014)

Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications. - Erica Tena-Sánchez; Javier Castro-Ramirez; Antonio J. Acosta 001 (PATMOS, 2014)

A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits. - Erica Tena-Sánchez; Javier Castro-Ramirez; Antonio J. Acosta 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Programmable ASICs for model predictive control. - Macarena C. Martínez-Rodríguez; Piedad Brox; Erica Tena; Antonio J. Acosta 001; Iluminada Baturone (ICIT, 2015)

DPA vulnerability analysis on Trivium stream cipher using an optimized power model. - Erica Tena-Sánchez; Antonio J. Acosta 001 (ISCAS, 2015)

Secure cryptographic hardware implementation issues for high-performance applications. - Erica Tena-Sánchez; Antonio J. Acosta 001; Juan Núñez 002 (PATMOS, 2016)

Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions. - Piedad Brox; Macarena C. Martínez-Rodríguez; Erica Tena-Sánchez; Iluminada Baturone; Antonio J. Acosta 001 (Int. J. Circuit Theory Appl., 2016)

Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview. - Antonio J. Acosta 001; Tommaso Addabbo; Erica Tena-Sánchez (Int. J. Circuit Theory Appl., 2017)

Power and Energy Issues on Lightweight Cryptography. - Antonio J. Acosta 001; Erica Tena-Sánchez; Carlos Jesús Jiménez-Fernández; Javier M. Mora-Merchan (J. Low Power Electron., 2017)

Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. - Erica Tena-Sánchez; Ignacio M. Delgado-Lozano; Juan Núñez 002; Antonio J. Acosta 001 (DCIS, 2018)

Effect of Temperature Variation in Experimental DPA and DEMA Attacks. - Erica Tena-Sánchez; Antonio J. Acosta 001 (PATMOS, 2018)

Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks. - Erica Tena-Sánchez; Antonio J. Acosta 001 (Int. J. Circuit Theory Appl., 2019)

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Ricardo Chaves; Manuel Valencia-Barrero; Antonio Acosta-Jiménez; Carlos Jesús Jiménez-Fernández (ISCAS, 2020)

Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies. - Ignacio M. Delgado-Lozano; Erica Tena-Sánchez; Juan Núñez 002; Antonio J. Acosta 001 (ACM J. Emerg. Technol. Comput. Syst., 2020)

Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; José Miguel Mora-Gutierrez; Manuel Valencia-Barrero; Carlos Jesús Jiménez-Fernández (IEEE Access, 2021)

Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; José Miguel Mora-Gutierrez; Manuel Valencia-Barrero; Carlos Jesús Jiménez-Fernández (Sensors, 2021)

Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices. - Ignacio M. Delgado-Lozano; Erica Tena-Sánchez; Juan Núñez 002; Antonio J. Acosta 001 (IEEE Trans. Emerg. Top. Comput., 2021)

Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Antonio J. Acosta 001; Carlos Jesús Jiménez-Fernández; Ricardo Chaves (IEEE Access, 2022)

Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs. - Ignacio M. Delgado-Lozano; Erica Tena-Sánchez; Juan Núñez 002; Antonio J. Acosta 001 (IEEE Embed. Syst. Lett., 2022)

A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem. - Eros Camacho-Ruiz; Santiago Sánchez-Solano; Macarena C. Martínez-Rodríguez; Erica Tena-Sánchez; Piedad Brox (DCIS, 2023)

A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks. - Virginia Zúñiga-González; Erica Tena-Sánchez; Antonio J. Acosta 001 (DCIS, 2023)

Cryptographic Security Through a Hardware Root of Trust. - Luis F. Rojas-Muñoz; Santiago Sánchez-Solano; Macarena C. Martínez-Rodríguez; Eros Camacho-Ruiz; Pablo Navarro-Torrero; Apurba Karmakar; Carlos Fernández García; Erica Tena-Sánchez; Francisco Eugenio Potestad-Ordóñez; Alejandro Casado-Galán; Pau Ortega-Castro; Antonio Acosta-Jiménez; et al. (ARC, 2024)

Electromagnetic Fault Injection Attack Methodology against AES Hardware Implementation. - Alejandro Casado-Galán; Francisco Eugenio Potestad-Ordóñez; Antonio J. Acosta 001; Erica Tena-Sánchez (DCIS, 2024)

Hardware implementations, SCA/FIA attacks, and countermeasures for the ASCON AEAD cipher: a review. - Miguel Martín-González; Erica Tena-Sánchez; F. Eugenio Potestad Ordóñez; Antonio J. Acosta 001 (DCIS, 2024)

Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Virginia Zúñiga-González; Antonio J. Acosta 001 (DSD, 2024)

Protecting FPGA-Based Cryptohardware Implementations from Fault Attacks Using ADCs. - Francisco Eugenio Potestad-Ordóñez; Alejandro Casado-Galán; Erica Tena-Sánchez (Sensors, 2024)

TERORO - Transient Effect Ring Oscillator and Ring Oscillator Configurable Hybrid PUF. - Alejandro Casado-Galán; J. Núñez-Martínez; Erica Tena-Sánchez; Francisco Eugenio Potestad-Ordóñez; Antonio J. Acosta 001 (SMACD, 2025)