A layout verification system for analog bipolar integrated circuits. - Erich Barke (DAC, 1983)

A technology independent block extraction algorithm. - F. Luellau; T. Hoepken; Erich Barke (DAC, 1984)

Figurenorientierte boolesche Maskenoperationen für die Layout-Prüfung integrierter Schaltungen / Polygon-based boolean mask operations to be used in IC design rule checking. - Erich Barke (Elektron. Rechenanlagen, 1984)

A Network Comparison Algorithm for Layout Verification of Integrated Circuits. - Erich Barke (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

Resistance calculation from mask artwork data by finite element method. - Erich Barke (DAC, 1985)

FERKEL: Technologieunabhängiges direktivengesteuertes Programmsystem zur Entwurfsregelnprüfung. - Erich Barke (Angew. Inform., 1985)

Line-to-ground capacitance calculation for VLSI: a comparison. - Erich Barke (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

A formal approach to nonlinear analog circuit verification. - Lars Hedrich; Erich Barke (ICCAD, 1995)

Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. - Carsten Borchers; Lars Hedrich; Erich Barke (DAC, 1996)

PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit Extractor. - Frank Scherber; Erich Barke; Wolfgang Meier (ED&TC, 1996)

A Universal CLA Adder Generator for SRAM-Based FPGAs. - Jörn Stohmann; Erich Barke (FPL, 1996)

Hierarchical partitioning. - Dirk Behrens; Klaus Harbich; Erich Barke (ICCAD, 1996)

Design driven partitioning. - Dirk Behrens; Erich Barke; Robert Tolkiehn (ASP-DAC, 1997)

A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs. - Jörn Stohmann; Erich Barke (ICCD, 1997)

A new approach to fault emulation. - Reza Sedaghat-Maman; Erich Barke (IEEE International Workshop on Rapid System Prototyping, 1997)

Real Time Fault Injection Using Logic Emulators. - Reza Sedaghat-Maman; Erich Barke (ASP-DAC, 1998)

A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. - Lars Hedrich; Erich Barke (DATE, 1998)

Path Verification Using Boolean Satisfiability. - Matthias Ringe; Thomas Lindenkreuz; Erich Barke (DATE, 1998)

An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. - Jörn Stohmann; Klaus Harbich; Markus Olbrich; Erich Barke (FPL, 1998)

An extended bipolar transistor model for substrate crosstalk analysis. - M. Klemme; Erich Barke (CICC, 1999)

A Universal Module Generator for LUT-Based FPGAs. - Joerg Abke; Erich Barke; Jörn Stohmann (IEEE International Workshop on Rapid System Prototyping, 1999)

A Case Study: Logic Emulation - Pitfalls and Solutions. - Klaus Harbich; Jörn Stohmann; Erich Barke; Ludwig Schwoerer (IEEE International Workshop on Rapid System Prototyping, 1999)

A current driven routing and verification methodology for analog applications. - Thorsten Adler; Hiltrud Brocke; Lars Hedrich; Erich Barke (DAC, 2000)

Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. - Thorsten Adler; Erich Barke (DATE, 2000)

Static Timing Analysis Taking Crosstalk into Account. - Matthias Ringe; Thomas Lindenkreuz; Erich Barke (DATE, 2000)

CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs. - Joerg Abke; Erich Barke (FPL, 2000)

PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. - Andreas Herrmann; Erich Barke; Mathias Silvant; Jürgen Schlöffel (PATMOS, 2000)

Architecture driven partitioning. - Joachim Küter; Erich Barke (DATE, 2001)

An improved hierarchical classification algorithm for structural analysis of integrated circuits. - Markus Olbrich; Achim Rein; Erich Barke (DATE, 2001)

A New Placement Method for Direct Mapping into LUT-Based FPGAs. - Joerg Abke; Erich Barke (FPL, 2001)

PuMA++: From Behavioral Specification to Multi-FPGA-Prototype. - Klaus Harbich; Erich Barke (FPL, 2001)

CHIPDESIGN - A Novel Project-oriented Microelectronics Course. - Mark Bernd Kulaczewski; Stefan Zimmerman; Erich Barke; Peter Pirsch (MSE, 2001)

On Discrete Modeling and Model Checking for Nonlinear Analog Systems. - Walter Hartong; Lars Hedrich; Erich Barke (CAV, 2002)

Model checking algorithms for analog verification. - Walter Hartong; Lars Hedrich; Erich Barke (DAC, 2002)

A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs . - Joerg Abke; Erich Barke (DATE, 2002)

An Approach to Model Checking for Nonlinear Analog Systems. - Walter Hartong; Lars Hedrich; Erich Barke (DATE, 2002)

Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. - Ralf Popp; Joerg Oehmen; Lars Hedrich; Erich Barke (DATE, 2002)

Analog circuit sizing based on formal methods using affine arithmetic. - Andreas C. Lemke; Lars Hedrich; Erich Barke (ICCAD, 2002)

An Upper Bound for 3D Slicing Floorplans. - Silke Salewski; Erich Barke (ASP-DAC/VLSI Design, 2002)

Placing substrate contacts into mixed-signal circuits controlling circuit performance. - Andreas Hermann 006; Markus Olbrich; Erich Barke (CICC, 2003)

Substrate Modeling and Noise Reduction in Mixed-Signal Circuits. - Andreas Hermann 006; Markus Olbrich; Erich Barke (VLSI-SOC, 2003)

Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. - Lutz Näthke; Volodymyr Burkhay; Lars Hedrich; Erich Barke (DATE, 2004)

Placement Using a Localization Probability Model (LPM). - Markus Olbrich; Erich Barke (DATE, 2004)

Wirelength Reduction Using 3-D Physical Design. - Idris Kaya; Silke Salewski; Markus Olbrich; Erich Barke (PATMOS, 2004)

Routing of analog busses with parasitic symmetry. - Lars A. Schreiner; Markus Olbrich; Erich Barke; Volker Meyer zu Bexten (ISPD, 2005)

Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. - Darius Grabowski; Daniel Platte; Lars Hedrich; Erich Barke (FAC, 2005)

Using Sequential Equations to Improve Efficiency and Robustness. - Daniel Platte; Shangjing Jing; Ralf Sommer; Erich Barke (FDL, 2006)

Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models. - Jan Torben Weinkopf; Klaus Harbich; Erich Barke (FPL, 2006)

Semi-symbolic modeling and simulation of circuits and systems. - Darius Grabowski; Christoph Grimm 001; Erich Barke (ISCAS, 2006)

Ein Verfahren zur effizienten Analyse von Schaltungen mit Parametervarianzen. - Darius Grabowski; Christoph Grimm 001; Erich Barke (MBMV, 2006)

Vermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen. - Ralf Klausen; Lars Hedrich; Erich Barke (MBMV, 2006)

Ansätze zur Verbesserung der Simulationsperformance automatisch generierter analoger Verhaltensmodelle. - Daniel Platte; Shangjing Jing; Ralf Sommer; Erich Barke (MBMV, 2006)

Efficient Modeling Techniques for Dynamic Voltage Drop Analysis. - Hedi Harizi; Robert HauBler; Markus Olbrich; Erich Barke (DAC, 2007)

CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. - Min Zhang; Markus Olbrich; David Seider; Martin Frerichs; Harald Kinzelbach; Erich Barke (DATE, 2007)

Range Arithmetics to Speed up Reachability Analysis of Analog Systems. - Darius Grabowski; Markus Olbrich; Christoph Grimm 001; Erich Barke (FDL, 2007)

Incremental Fault Emulation. - Jan Torben Weinkopf; Klaus Harbich; Erich Barke (FPL, 2007)

Robust wiring networks for DfY considering timing constraints. - Philipp V. Panitz; Markus Olbrich; Erich Barke; Jürgen Koehl (ACM Great Lakes Symposium on VLSI, 2007)

Algorithms for automatic length compensation of busses in analog integrated circuits. - Matthew A. Smith; Lars A. Schreiner; Erich Barke; Volker Meyer zu Bexten (ISPD, 2007)

Analog circuit simulation using range arithmetics. - Darius Grabowski; Markus Olbrich; Erich Barke (ASP-DAC, 2008)

Distribution arithmetic for stochastical analysis. - Markus Olbrich; Erich Barke (ASP-DAC, 2008)

Determining the Technical Complexity of Integrated Circuits. - Peter Leppelt; Erich Barke (DATE, 2008)

A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. - Thomas Jambor; Daniel Zaum; Markus Olbrich; Erich Barke (DDECS, 2008)

Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). - Stefan Hoelldampf; Daniel Zaum; Markus Olbrich; Erich Barke; Ingmar Neumann; Sebastian Schmidt 004 (FDL, 2008)

Considering possible opens in non-tree topology wire delay calculation. - Philipp V. Panitz; Markus Olbrich; Erich Barke; Markus Bühler; Jürgen Koehl (ACM Great Lakes Symposium on VLSI, 2008)

The PRAISE approach for accelerated transient analysis applied to wire models. - Daniel Zaum; Stefan Hoelldampf; Markus Olbrich; Erich Barke; Ingmar Neumann; Sebastian Schmidt 004 (BMAS, 2009)

Formal approaches to analog circuit verification. - Erich Barke; Darius Grabowski; Helmut Graeb; Lars Hedrich; Stefan Heinen; Ralf Popp; Sebastian Steinhorst; Yifan Wang 001 (DATE, 2009)

Fast dynamic power estimation considering glitch filtering. - Lei Wang; Markus Olbrich; Erich Barke; Thomas Büchner; Markus Bühler (SoCC, 2009)

Towards Abstract Analysis Techniques for Range Based System Simulations. - Florian Schupfer; Christoph Grimm 001; Markus Olbrich; Michael Kärgel; Erich Barke (FDL, 2010)

An Accelerated Mixed-Signal Simulation Kernel for SystemC. - Daniel Zaum; Stefan Hoelldampf; Markus Olbrich; Erich Barke; Ingmar Neumann (FDL, 2010)

3D floorplanning considering vertically aligned rectilinear modules using T∗-tree. - Artur Quiring; Marc Lindenberg; Markus Olbrich; Erich Barke (3DIC, 2011)

A theoretical probabilistic simulation framework for dynamic power estimation. - Lei Wang; Markus Olbrich; Erich Barke; Thomas Büchner; Markus Bühler; Philipp V. Panitz (ICCAD, 2011)

Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation. - Stefan Hoelldampf; Daniel Zaum; Markus Olbrich; Erich Barke (ICCD, 2011)

A gate sizing method for glitch power reduction. - Lei Wang; Markus Olbrich; Erich Barke; Thomas Büchner; Markus Bühler; Philipp V. Panitz (SoCC, 2011)

A Statistical Learning Based Modeling Approach and Its Application in Leakage Library Characterization. - Min Zhang; R. Häußler; Markus Olbrich; Harald Kinzelbach; Erich Barke (VLSI Design, 2011)

Efficient generation of analog circuit models for accelerated mixed-signal simulation. - Stefan Hoelldampf; Hyun-Sek Lukas Lee; Daniel Zaum; Markus Olbrich; Erich Barke (SoCC, 2012)

Improving 3D-Floorplanning using smart selection operations in meta-heuristic optimization. - Artur Quiring; Markus Olbrich; Erich Barke (3DIC, 2013)

Application of Mission Profiles to enable cross-domain constraint-driven design. - C. Katzschke; M.-P. Sohn; Markus Olbrich; Volker Meyer zu Bexten; Markus Tristl; Erich Barke (DATE, 2014)

Simulation Based Verification with Range Based Signal Representations for Mixed-Signal Systems. - Michael Kärgel; Markus Olbrich; Erich Barke (SBCCI, 2014)

Automated generation of hybrid system models for reachability analysis of nonlinear analog circuits. - Hyun-Sek Lukas Lee; Matthias Althoff; Stefan Hoelldampf; Markus Olbrich; Erich Barke (ASP-DAC, 2015)

Split and merge strategies for solving uncertain equations using affine arithmetic. - Oliver Scharf; Markus Olbrich; Erich Barke (SimuTools, 2015)

Fast global interconnnect driven 3D floorplanning. - Artur Quiring; Markus Olbrich; Erich Barke (VLSI-SoC, 2015)

Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis. - Erich Barke; Andreas Furtig; Georg Glaeser; Christoph Grimm 001; Lars Hedrich; Stefan Heinen; Eckhard Hennig; Hyun-Sek Lukas Lee; Wolfgang Nebel; Gregor Nitsche; Markus Olbrich; Carna Radojicic; et al. (DATE, 2016)

STP - A Quadratic VLSI Placement Tool Using Graphic Processing Units. - Bjorn Bredthauer; Markus Olbrich; Erich Barke (ISPDC, 2018)

Hierarchical Verification of AMS Systems With Affine Arithmetic Decision Diagrams. - Carna Zivkovic; Christoph Grimm 001; Markus Olbrich; Oliver Scharf; Erich Barke (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)