A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet. - Erich F. Haratsch; Kamran Azadet (CICC, 2000)

Pipelined reduced-state sequence estimation. - Erich F. Haratsch; Kamran Azadet (GLOBECOM, 2000)

Reduced-State Sequence Estimation with Tap-Selectable Decision-Feedback. - Erich F. Haratsch; Andrew J. Blanksby; Kamran Azadet (ICC (1), 2000)

High-speed reduced-state sequence estimation. - Erich F. Haratsch; Kamran Azadet (ISCAS, 2000)

A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet. - Erich F. Haratsch; Kamran Azadet (IEEE J. Solid State Circuits, 2001)

Equalization and FEC techniques for optical transceivers. - Kamran Azadet; Erich F. Haratsch; Helen Kim; Fadi Saibi; Jeffrey H. Saunders; Michael Shaffer; Leilei Song; Meng-Lin Yu (IEEE J. Solid State Circuits, 2002)

Trellis-based detection for high-speed data communications. - Erich F. Haratsch (2004)

Digital signal processing in read channels. - Erich F. Haratsch; Z. A. Keirn (CICC, 2005)

VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel. - Hao Zhong 006; Tong Zhang 002; Erich F. Haratsch (CICC, 2006)

High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor. - Hao Zhong 006; Tong Zhang 002; Erich F. Haratsch (ISCAS, 2006)

A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders. - Ruwan N. S. Ratnayake; Erich F. Haratsch; Gu-Yeon Wei (GLOBECOM, 2007)

Serial Sum-Product Architecture for Low-Density Parity-Check Codes. - Ruwan N. S. Ratnayake; Erich F. Haratsch; Gu-Yeon Wei (ICCCN, 2007)

FPGA-Based Solid-State Drive Prototyping Platform. - Yu Cai 001; Erich F. Haratsch; Mark P. McCartney; Ken Mai (FCCM, 2011)

FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). - Yu Cai 001; Erich F. Haratsch; Mark P. McCartney; Mudit Bhargava; Ken Mai (FPGA, 2011)

Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. - Yu Cai 001; Erich F. Haratsch; Onur Mutlu; Ken Mai (DATE, 2012)

Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime. - Yu Cai 001; Gulay Yalcin; Onur Mutlu; Erich F. Haratsch; Adrián Cristal; Osman S. Ünsal; Ken Mai (ICCD, 2012)

Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling. - Yu Cai 001; Erich F. Haratsch; Onur Mutlu; Ken Mai (DATE, 2013)

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation. - Yu Cai 001; Onur Mutlu; Erich F. Haratsch; Ken Mai (ICCD, 2013)

Noise modeling and capacity analysis for NAND flash memories. - Qing Li 002; Anxiao Jiang; Erich F. Haratsch (ISIT, 2014)

Neighbor-cell assisted error correction for MLC NAND flash memories. - Yu Cai 001; Gulay Yalcin; Onur Mutlu; Erich F. Haratsch; Osman S. Unsal; Adrián Cristal; Ken Mai (SIGMETRICS, 2014)

Joint decoding of content-replication codes for flash memories. - Qing Li 002; Huan Chang; Anxiao Jiang; Erich F. Haratsch (Allerton, 2015)

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery. - Yu Cai 001; Yixin Luo; Erich F. Haratsch; Ken Mai; Onur Mutlu (HPCA, 2015)

A study of polar codes for MLC NAND flash memories. - Yue Li 001; Hakim Alhussien; Erich F. Haratsch; Anxiao Andrew Jiang (ICNC, 2015)

Write process modeling in MLC flash memories using renewal theory. - Meysam Asadi; Erich F. Haratsch; Aleksandar Kavcic; Narayana P. Santhanam (ISIT, 2015)

Flash Memories: ISPP Renewal Theory and Flash Design Tradeoffs. - Meysam Asadi; Erich F. Haratsch; Aleksandar Kavcic; Narayana Prasad Santhanam (IEEE J. Sel. Areas Commun., 2016)

Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory. - Yixin Luo; Saugata Ghose; Yu Cai 001; Erich F. Haratsch; Onur Mutlu (IEEE J. Sel. Areas Commun., 2016)

Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques. - Yu Cai 001; Saugata Ghose; Yixin Luo; Ken Mai; Onur Mutlu; Erich F. Haratsch (HPCA, 2017)

Correcting errors by natural redundancy. - Anxiao Jiang; Pulakesh Upadhyaya; Erich F. Haratsch; Jehoshua Bruck (ITA, 2017)

Syndrome-coupled rate-compatible error-correcting codes. - Pengfei Huang 001; Yi Liu 052; Xiaojie Zhang; Paul H. Siegel; Erich F. Haratsch (ITW, 2017)

Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery. - Yu Cai 001; Saugata Ghose; Erich F. Haratsch; Yixin Luo; Onur Mutlu (CoRR, 2017)

Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives. - Yu Cai 001; Saugata Ghose; Erich F. Haratsch; Yixin Luo; Onur Mutlu (Proc. IEEE, 2017)

HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness. - Yixin Luo; Saugata Ghose; Yu Cai 001; Erich F. Haratsch; Onur Mutlu (HPCA, 2018)

Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory. - Yu Cai 001; Yixin Luo; Erich F. Haratsch; Ken Mai; Saugata Ghose; Onur Mutlu (CoRR, 2018)

Read Disturb Errors in MLC NAND Flash Memory. - Yu Cai 001; Yixin Luo; Saugata Ghose; Erich F. Haratsch; Ken Mai; Onur Mutlu (CoRR, 2018)

Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming. - Yu Cai 001; Saugata Ghose; Yixin Luo; Ken Mai; Onur Mutlu; Erich F. Haratsch (CoRR, 2018)

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation. - Yixin Luo; Saugata Ghose; Yu Cai 001; Erich F. Haratsch; Onur Mutlu (Proc. ACM Meas. Anal. Comput. Syst., 2018)

Syndrome-Coupled Rate-Compatible Error-Correcting Codes: Theory and Application. - Pengfei Huang 001; Yi Liu 052; Xiaojie Zhang; Paul H. Siegel; Erich F. Haratsch (IEEE Trans. Inf. Theory, 2020)