FPGA Interconnect Delay Fault Testing. - Erik Chmelar (ITC, 2003)

Subframe multiplexing for FPGA manufacturing test configuration. - Erik Chmelar (FPGA, 2004)

Minimizing the number of test configurations for FPGAs. - Erik Chmelar (ICCAD, 2004)

FPGA Bridging Fault Detection and Location via Differential I{DDQ}. - Erik Chmelar; Shahin Toutounchi (VTS, 2004)

Segmented Addressable Scan Architecture. - Ahmad A. Al-Yamani; Erik Chmelar; Mikhail Grinchuck (VTS, 2005)

Session Abstract. - Erik Chmelar; Edward J. McCluskey (VTS, 2006)

Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration. - Ahmad A. Al-Yamani; Narendra Devta-Prasanna; Erik Chmelar; M. Grinchuk; Arun Gunda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Inconsistent Fail due to Limited Tester Timing Accuracy. - Intaik Park; Donghwi Lee; Erik Chmelar; Edward J. McCluskey (VTS, 2008)