A Simulator of Homogeneous Multiprocessor Systems. - Erik H. D'Hollander; H. Simoens (ESC, 1983)

Implementation of An Automatic Program Partitioner on a Homogeneous Multiprocessor. - Erik H. D'Hollander; Johan Opsommer (ICPP, 1987)

Partitioning and Labeling of Index Sets in DO Loops with Constant Dependence Vectors. - Erik H. D'Hollander (ICPP (2), 1989)

Directed Taskgraph Scheduling Using Simulated Annealing. - Erik H. D'Hollander; Yves Devis (ICPP (2), 1991)

Partitioning and Labeling of Loops by Unimodular Transformations. - Erik H. D'Hollander (IEEE Trans. Parallel Distributed Syst., 1992)

Performance Modeling of Microkernel Thread Schedulers for Shared Memory Multiprocessors. - Wim Van de Velde; Johan Opsommer; Erik H. D'Hollander (PARLE, 1993)

Using Hammock Graphs to Eliminate Nonstructured Branch Statements. - Fubo Zhang; Erik H. D'Hollander (PARLE, 1993)

Extracting the Parallelism in Program with Unstructured Control Statements. - Fubo Zhang; Erik H. D'Hollander (ICPADS, 1994)

Enhancing Parallelism by Removing Cyclic Data Dependencies. - Fubo Zhang; Erik H. D'Hollander (PARLE, 1994)

PVM Code Generator for the Fortran Parallel Transformer. - Erik H. D'Hollander; Fubo Zhang (PDPTA, 1996)

Visualizing the Iteration Space in PEFPT. - Qi Wang; Yijun Yu; Erik H. D'Hollander (HPCN Europe, 1997)

The FORTRAN Parallel Transformer and its Programming. - Erik H. D'Hollander; Fubo Zhang; Qi Wang (Inf. Sci., 1998)

JPT: A Java Parallelization Tool. - Kristof Beyls; Erik H. D'Hollander; Yijun Yu (PVM/MPI, 1999)

Cache Remapping to Improve the Performance of Tiled Algorithms. - Kristof Beyls; Erik H. D'Hollander (Euro-Par, 2000)

Partitioning Loops with Variable Dependence Distances. - Yijun Yu; Erik H. D'Hollander (ICPP, 2000)

Compiler Generated Multithreading to Alleviate Memory Latency. - Kristof Beyls; Erik H. D'Hollander (J. Univers. Comput. Sci., 2000)

Visualizing the Impact of the Cache on Program Execution. - Yijun Yu; Kristof Beyls; Erik H. D'Hollander (IV, 2001)

Linear systems and associated problems - introduction. - Henk J. Sips; Ruud Sommerhalder; Erik H. D'Hollander (Parallel Comput., 2001)

Loop Parallelization using the 3D Iteration Space Visualizer. - Yijun Yu; Erik H. D'Hollander (J. Vis. Lang. Comput., 2001)

Reuse Distance-Based Cache Hint Selection. - Kristof Beyls; Erik H. D'Hollander (Euro-Par, 2002)

Visualization Enables the Programmer to Reduce Cache Misses. - Kristof Beyls; Erik H. D'Hollander; Yijun Yu (IASTED PDCS, 2002)

Platform-Independent Cache Optimization by Pinpointing Low-Locality Reuse. - Kristof Beyls; Erik H. D'Hollander (International Conference on Computational Science, 2004)

Non-Uniform Dependences Partitioned by Recurrence Chains. - Yijun Yu; Erik H. D'Hollander (ICPP, 2004)

Performance Visualizations using XML Representations. - Yijun Yu; Kristof Beyls; Erik H. D'Hollander (IV, 2004)

Using Hammock Graphs to Structure Programs. - Fubo Zhang; Erik H. D'Hollander (IEEE Trans. Software Eng., 2004)

RDVIS: A Tool that Visualizes the Causes of Low Locality and Hints Program Optimizations. - Kristof Beyls; Erik H. D'Hollander; Frederik Vandeputte (International Conference on Computational Science (2), 2005)

Generating cache hints for improved program efficiency. - Kristof Beyls; Erik H. D'Hollander (J. Syst. Archit., 2005)

Making XML document markup international. - Yijun Yu; Jianguo Lu; John Mylopoulos; Weiwei Sun 008; Jing-Hao Xue; Erik H. D'Hollander (Softw. Pract. Exp., 2005)

Intermediately executed code is the key to find refactorings that improve temporal data locality. - Kristof Beyls; Erik H. D'Hollander (Conf. Computing Frontiers, 2006)

Discovery of Locality-Improving Refactorings by Reuse Path Analysis. - Kristof Beyls; Erik H. D'Hollander (HPCC, 2006)

Parallel Computing with FPGAs - Concepts and Applications. - Erik H. D'Hollander; Dirk Stroobandt; Abdellah Touhafi (PARCO, 2007)

Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations. - Harald Devos; Kristof Beyls; Mark Christiaens; Jan M. Van Campenhout; Erik H. D'Hollander; Dirk Stroobandt (Trans. High Perform. Embed. Archit. Compil., 2007)

Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler. - Fabian Diet; Erik H. D'Hollander; Kristof Beyls; Harald Devos (DELTA, 2008)

High Performance Computing with FPGAs. - Erik H. D'Hollander; Kristof Beyls (High Performance Computing Workshop, 2008)

Refactoring Intermediately Executed Code to Reduce Cache Capacity Misses. - Kristof Beyls; Erik H. D'Hollander (J. Instr. Level Parallelism, 2008)

ParaFPGA: Parallel Computing with Flexible Hardware. - Erik H. D'Hollander; Dirk Stroobandt; Abdellah Touhafi (PARCO, 2009)

Refactoring for Data Locality. - Kristof Beyls; Erik H. D'Hollander (Computer, 2009)

Efficient memory management for hardware accelerated Java Virtual Machines. - Peter Bertels; Wim Heirman; Erik H. D'Hollander; Dirk Stroobandt (ACM Trans. Design Autom. Electr. Syst., 2009)

ParaFPGA 2011 - High Performance Computing with Multiple FPGAs: Design Methodology and Applications. - Erik H. D'Hollander; Dirk Stroobandt; Abdellah Touhafi (PARCO, 2011)

Performance and Programming Environment of a Combined GPU/FPGA Desktop. - Bruno da Silva 001; An Braeken; Erik H. D'Hollander; Abdellah Touhafi; Jan G. Cornelis; Jan Lemeire (High Performance Computing Workshop (2), 2012)

Performance and toolchain of a combined GPU/FPGA desktop (abstract only). - Bruno da Silva 001; An Braeken; Erik H. D'Hollander; Abdellah Touhafi; Jan G. Cornelis; Jan Lemeire (FPGA, 2013)

Comparing and combining GPU and FPGA accelerators in an image processing context. - Bruno da Silva 001; An Braeken; Erik H. D'Hollander; Abdellah Touhafi; Jan G. Cornelis; Jan Lemeire (FPL, 2013)

ParaFPGA 2013: Harnessing Programs, Power and Performance in Parallel FPGA applications. - Erik H. D'Hollander; Dirk Stroobandt; Abdellah Touhafi (PARCO, 2013)

Performance and Resource Modeling for FPGAs using High-Level Synthesis tools. - Bruno da Silva 001; An Braeken; Erik H. D'Hollander; Abdellah Touhafi (PARCO, 2013)

Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools. - Bruno da Silva 001; An Braeken; Erik H. D'Hollander; Abdellah Touhafi (Int. J. Reconfigurable Comput., 2013)

ParaFPGA15: Exploring threads and trends in programmable hardware. - Erik H. D'Hollander; Dirk Stroobandt; Abdellah Touhafi (PARCO, 2015)

High-Level Synthesis Optimization for Blocked Floating-Point Matrix Multiplication. - Erik H. D'Hollander (SIGARCH Comput. Archit. News, 2016)

Calling hardware procedures in a reconfigurable accelerator using RPC-FPGA. - Erik H. D'Hollander; Bruno Chevalier; Koen De Bosschere (FPT, 2017)

ParaFPGA 2017: Enlarging the Scope of Parallel Programming with FPGAs. - Erik H. D'Hollander; Abdellah Touhafi (PARCO, 2017)

Heterogeneous Cloud Computing: Design Methodology to Combine Hardware Accelerators. - Bruno da Silva 001; Jan G. Cornelis; An Braeken; Erik H. D'Hollander; Jan Lemeire; Abdellah Touhafi (Cloudtech, 2018)

Empowering Parallel Computing with Field Programmable Gate Arrays. - Erik H. D'Hollander (PARCO, 2019)

Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL. - Thomas Faict; Erik H. D'Hollander; Bart Goossens (Algorithms, 2019)

ZyPy: Intercepting NumPy operations for acceleration on FPGAs. - Gerbrand De Laender; Erik H. D'Hollander (HEART, 2023)

Exploring Large Language Models for Verilog Hardware Design Generation. - Erik H. D'Hollander; Ewout Danneels; Karel-Brecht Decorte; Senne Loobuyck; Arne Vanheule; Ian Van Kets; Dirk Stroobandt (IPDPS (Workshops), 2024)