A controller testability analysis and enhancement technique. - Xinli Gu; Erik Larsson; Krzysztof Kuchcinski; Zebo Peng (ED&TC, 1997)

Time of arrival estimation of narrowband TDMA signals for mobile positioning. - Sven Fischer; Hans Grubeck; Ari Kangas; Havish Koorapaty; Erik Larsson; Patrik Lundqvist (PIMRC, 1998)

Helpdesk.Drew.Edu: Home Growing a Helpdesk Solution Using Open-Source Technology. - John Saul; Betsy Black; Erik Larsson (SIGUCCS, 2000)

An Integrated System-Level Design for Testability Methodology. - Erik Larsson (2000)

Test Scheduling and Scan-Chain Division under Power Constraint. - Erik Larsson; Zebo Peng (Asian Test Symposium, 2001)

An integrated system-on-chip test framework. - Erik Larsson; Zebo Peng (DATE, 2001)

The Design and Optimization of SOC Test Solutions. - Erik Larsson; Zebo Peng; Gunnar Carlsson (ICCAD, 2001)

Integrated Test Scheduling, Test Parallelization and TAMDesign. - Erik Larsson; Klas Arvidsson; Hideo Fujiwara; Zebo Peng (Asian Test Symposium, 2002)

Power constrained preemptive TAM scheduling. - Erik Larsson; Hideo Fujiwara (ETW, 2002)

An Integrated Framework for the Design and Optimization of SOC Test Solutions. - Erik Larsson; Zebo Peng (J. Electron. Test., 2002)

Optimal System-on-Chip Test Scheduling. - Erik Larsson; Hideo Fujiwara (Asian Test Symposium, 2003)

SOC Test Time Minimization Under Multiple Constraints. - Julien Pouget; Erik Larsson; Zebo Peng (Asian Test Symposium, 2003)

Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip. - Anders Larsson; Erik Larsson; Petru Eles; Zebo Peng (DFT, 2003)

An efficient approach to SoC wrapper design, TAM configuration and test scheduling. - Julien Pouget; Erik Larsson; Zebo Peng; Marie-Lise Flottes; Bruno Rouzeyre (ETW, 2003)

A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling. - Erik Larsson; Zebo Peng (ITC, 2003)

Test Resource Partitioning and Optimization for SOC Designs. - Erik Larsson; Hideo Fujiwara (VTS, 2003)

An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint. - Stina Edbom; Erik Larsson (Asian Test Symposium, 2004)

Integrating Core Selection in the SOC Test Solution Design-Flow. - Erik Larsson (ITC, 2004)

Student-oriented examination in a computer architecture course. - Erik Larsson; Anders Larsson (ITiCSE, 2004)

Defect-Aware SOC Test Scheduling. - Erik Larsson; Julien Pouget; Zebo Peng (VTS, 2004)

Preemptive System-on-Chip Test Scheduling. - Erik Larsson; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2004)

Efficient test solutions for core-based designs. - Erik Larsson; Klas Arvidsson; Hideo Fujiwara; Zebo Peng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

SOC Test Scheduling with Test Set Sharing and Broadcasting. - Anders Larsson; Erik Larsson; Petru Eles; Zebo Peng (Asian Test Symposium, 2005)

Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip. - Anders Larsson; Erik Larsson; Petru Eles; Zebo Peng (DSD, 2005)

Test scheduling for modular SOCs in an abort-on-fail environment. - Urban Ingelsson; Sandeep Kumar Goel; Erik Larsson; Erik Jan Marinissen (ETS, 2005)

Remote boundary-scan system test control for the ATCA standard. - David Bäckström; Gunnar Carlsson; Erik Larsson (ITC, 2005)

Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint. - Erik Larsson; Stina Edbom (VLSI-SoC, 2005)

Abort-on-Fail Based Test Scheduling. - Erik Larsson; Julien Pouget; Zebo Peng (J. Electron. Test., 2005)

Multiple-Constraint Driven System-on-Chip Test Time Optimization. - Julien Pouget; Erik Larsson; Zebo Peng (J. Electron. Test., 2005)

Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling. - Soheil Samii; Erik Larsson; Krishnendu Chakrabarty; Zebo Peng (ITC, 2006)

Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process. - Erik Larsson; Zebo Peng (IEEE Trans. Computers, 2006)

System-on-chip test scheduling with reconfigurable core wrappers. - Erik Larsson; Hideo Fujiwara (IEEE Trans. Very Large Scale Integr. Syst., 2006)

An Architecture for Combined Test Data Compression and Abort-on-Fail Test. - Erik Larsson; Jon Persson (ASP-DAC, 2007)

Test quality analysis and improvement for an embedded asynchronous FIFO. - Tobias Dubois; Erik Jan Marinissen; Mohamed Azimane; Paul Wielage; Erik Larsson; Clemens Wouters (DATE, 2007)

Optimized integration of test compression and sharing for SOC testing. - Anders Larsson; Erik Larsson; Petru Eles; Zebo Peng (DATE, 2007)

A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing. - Anders Larsson; Erik Larsson; Petru Eles; Zebo Peng (DDECS, 2007)

Protocol requirements in an SJTAG/IJTAG environment. - Gunnar Carlsson; Johan Holmqvist; Erik Larsson (ITC, 2007)

What impacts course evaluation? - Erik Larsson; Mehdi Amirijoo; Daniel Karlsson; Petru Eles (ITiCSE, 2007)

HeliCis: a DNA motif discovery tool for colocalized motif pairs with periodic spacing. - Erik Larsson; Per Lindahl; Petter Mostad (BMC Bioinform., 2007)

Test data truncation for test quality maximisation under ATE memory depth constraint. - Erik Larsson; Stina Edbom (IET Comput. Digit. Tech., 2007)

Core-Level Compression Technique Selection and SOC Test Architecture Design. - Anders Larsson; Xin Zhang; Erik Larsson; Krishnendu Chakrabarty (ATS, 2008)

Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns. - Anders Larsson; Erik Larsson; Krishnendu Chakrabarty; Petru Eles; Zebo Peng (DATE, 2008)

SOC Test Optimization with Compression-Technique Selection. - Anders Larsson; Xin Zhang; Erik Larsson; Krishnendu Chakrabarty (ITC, 2008)

A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling. - Erik Larsson; Zebo Peng (J. Electron. Test., 2008)

Architecture for integrated test data compression and abort-on-fail testing in a multi-site environment. - Erik Larsson (IET Comput. Digit. Tech., 2008)

Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling. - Soheil Samii; Mikko Selkälä; Erik Larsson; Krishnendu Chakrabarty; Zebo Peng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

On Scan Chain Diagnosis for Intermittent Faults. - Dan Adolfsson; Joanna Siew; Erik Jan Marinissen; Erik Larsson (Asian Test Symposium, 2009)

Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips. - Mikael Väyrynen; Virendra Singh; Erik Larsson (DATE, 2009)

On Minimization of Peak Power for Scan Circuit during Test. - Jaynarayan T. Tudu; Erik Larsson; Virendra Singh; Vishwani D. Agrawal (ETS, 2009)

Efficient Embedding of Deterministic Test Data. - Mudassar Majeed; Daniel Ahlstrom; Urban Ingelsson; Gunnar Carlsson; Erik Larsson (Asian Test Symposium, 2010)

Test Time Analysis for IEEE P1687. - Farrokh Ghani Zadegan; Urban Ingelsson; Gunnar Carlsson; Erik Larsson (Asian Test Symposium, 2010)

Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. - Pramod Subramanyan; Virendra Singh; Kewal K. Saluja; Erik Larsson (DATE, 2010)

Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing. - Dimitar Nikolov; Urban Ingelsson; Virendra Singh; Erik Larsson (DELTA, 2010)

Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding. - Pramod Subramanyan; Virendra Singh; Kewal K. Saluja; Erik Larsson (DSN, 2010)

A distributed architecture to check global properties for post-silicon debug. - Erik Larsson; Bart Vermeulen; Kees Goossens (ETS, 2010)

Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. - Jaynarayan T. Tudu; Erik Larsson; Virendra Singh; Hideo Fujiwara (ETS, 2010)

Thermal aware test scheduling for stacked multi-chip-modules. - N. S. Vinay; Indira Rawat; Erik Larsson; Manoj Singh Gaur; Virendra Singh (EWDTS, 2010)

Energy-efficient redundant execution for chip multiprocessors. - Pramod Subramanyan; Virendra Singh; Kewal K. Saluja; Erik Larsson (ACM Great Lakes Symposium on VLSI, 2010)

Graph theoretic approach for scan cell reordering to minimize peak shift power. - Jaynarayan T. Tudu; Erik Larsson; Virendra Singh; Hideo Fujiwara (ACM Great Lakes Symposium on VLSI, 2010)

Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints. - Farrokh Ghani Zadegan; Urban Ingelsson; Golnaz Asani; Gunnar Carlsson; Erik Larsson (Asian Test Symposium, 2011)

Design automation for IEEE P1687. - Farrokh Ghani Zadegan; Urban Ingelsson; Gunnar Carlsson; Erik Larsson (DATE, 2011)

Measurement point selection for in-operation wear-out monitoring. - Urban Ingelsson; Shih-Yen Chang; Erik Larsson (DDECS, 2011)

Level of confidence evaluation and its usage for Roll-back Recovery with Checkpointing optimization. - Dimitar Nikolov; Urban Ingelsson; Virendra Singh; Erik Larsson (DSN Workshops, 2011)

Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. - Pramod Subramanyan; Virendra Singh; Kewal K. Saluja; Erik Larsson (ICCD, 2011)

Accessing Embedded DfT Instruments with IEEE P1687. - Erik Larsson; Farrokh Ghani Zadegan (Asian Test Symposium, 2012)

Fault management in an IEEE P1687 (IJTAG) environment. - Erik Larsson; Konstantin Sibin (DDECS, 2012)

Re-using chip level DFT at board level. - Xinli Gu; Jeff Rearick; Bill Eklow; Martin Keim; Jun Qian; Artur Jutman; Krishnendu Chakrabarty; Erik Larsson (ETS, 2012)

Design principles for four branch downlink MIMO for long term HSPA evolution. - Sairamesh Nammi; Bo Göransson; Erik Larsson; Qingyu Miao (ICC, 2012)

Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias. - Breeta SenGupta; Urban Ingelsson; Erik Larsson (VLSI Design, 2012)

miRcode: a map of putative microRNA target sites in the long non-coding transcriptome. - Ashwini Jeggari; Debora S. Marks; Erik Larsson (Bioinform., 2012)

Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687. - Farrokh Ghani Zadegan; Urban Ingelsson; Erik Larsson; Gunnar Carlsson (IEEE Des. Test Comput., 2012)

Scheduling Tests for 3D Stacked Chips under Power Constraints. - Breeta SenGupta; Urban Ingelsson; Erik Larsson (J. Electron. Test., 2012)

Access Time Analysis for IEEE P1687. - Farrokh Ghani Zadegan; Urban Ingelsson; Gunnar Carlsson; Erik Larsson (IEEE Trans. Computers, 2012)

Special session 9B: Embedded tutorial embedded DfT instrumentation: Design, access, retargeting and case studies. - Erik Larsson (VTS, 2013)

Design, Verification, and Application of IEEE 1687. - Farrokh Ghani Zadegan; Erik Larsson; Artur Jutman; Sergei Devadze; Rene Krenz-Baath (ATS, 2014)

Fault injection and fault handling: An MPSoC demonstrator using IEEE P1687. - Kim Petersén; Dimitar Nikolov; Urban Ingelsson; Gunnar Carlsson; Farrokh Ghani Zadegan; Erik Larsson (IOLTS, 2014)

Robustness of TAP-based scan networks. - Farrokh Ghani Zadegan; Gunnar Carlsson; Erik Larsson (ITC, 2014)

Test planning and test access mechanism design for stacked chips using ILP. - Breeta SenGupta; Erik Larsson (VTS, 2014)

Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems. - Dimitar Nikolov; Urban Ingelsson; Virendra Singh; Erik Larsson (Microelectron. Reliab., 2014)

On the testability of IEEE 1687 networks. - Riccardo Cantoro; Mehrdad Montazeri; Matteo Sonza Reorda; Farrokh Ghani Zadegan; Erik Larsson (ATS, 2015)

Access time minimization in IEEE 1687 networks. - Rene Krenz-Baath; Farrokh Ghani Zadegan; Erik Larsson (ITC, 2015)

No Fault Found: The root cause. - Erik Larsson; Bill Eklow; Scott Davidsson; Rob Aitken; Artur Jutman; Christophe Lotz (VTS, 2015)

Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption. - Urban Ingelsson; Sandeep Kumar Goel; Erik Larsson; Erik Jan Marinissen (IEEE Trans. Computers, 2015)

Maximizing level of confidence for non-equidistant Checkpointing. - Dimitar Nikolov; Erik Larsson (ASP-DAC, 2016)

On the diagnostic analysis of IEEE 1687 networks. - Riccardo Cantoro; Mehrdad Montazeri; Matteo Sonza Reorda; Farrokh Ghani Zadegan; Erik Larsson (ETS, 2016)

A self-reconfiguring IEEE 1687 network for fault monitoring. - Farrokh Ghani Zadegan; Dimitar Nikolov; Erik Larsson (ETS, 2016)

Compressor design for silicon debug. - Jing Zhang; Lars-Johan Fritz; Liang Liu 002; Erik Larsson (ETS, 2016)

Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks. - Riccardo Cantoro; Mehrdad Montazeri; Matteo Sonza Reorda; Farrokh Ghani Zadegan; Erik Larsson (IOLTS, 2016)

A suite of IEEE 1687 benchmark networks. - Anton Tsertov; Artur Jutman; Sergei Devadze; Matteo Sonza Reorda; Erik Larsson; Farrokh Ghani Zadegan; Riccardo Cantoro; Mehrdad Montazeri; Rene Krenz-Baath (ITC, 2016)

Upper-bound computation for optimal retargeting in IEEE1687 networks. - Farrokh Ghani Zadegan; Rene Krenz-Baath; Erik Larsson (ITC, 2016)

Accessing on-chip instruments through the life-time of systems. - Erik Larsson; Farrokh Ghani Zadegan (LATS, 2016)

In-field system-health monitoring based on IEEE 1687. - Farrokh Ghani Zadegan; Dimitar Nikolov; Erik Larsson (SoCC, 2016)

Optimizing the Level of Confidence for Multiple Jobs. - Dimitar Nikolov; Erik Larsson (IEEE Trans. Computers, 2016)

BASTION: Board and SoC test instrumentation for ageing and no failure found. - Artur Jutman; Christophe Lotz; Erik Larsson; Matteo Sonza Reorda; Maksim Jenihhin; Jaan Raik; Hans G. Kerkhoff; Rene Krenz-Baath; Piet Engelke (DATE, 2017)

Test Planning for Core-based Integrated Circuits under Power Constraints. - Breeta SenGupta; Dimitar Nikolov; Urban Ingelsson; Erik Larsson (J. Electron. Test., 2017)

Clustered checkpointing: Maximizing the level of confidence for non-equidistant checkpointing. - Dimitar Nikolov; Erik Larsson (Integr., 2017)

Editorial. - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Test of Reconfigurable Modules in Scan Networks. - Riccardo Cantoro; Farrokh Ghani Zadegan; Marco Palena; Paolo Pasini; Erik Larsson; Matteo Sonza Reorda (IEEE Trans. Computers, 2018)

On-Chip Fault Monitoring Using Self-Reconfiguring IEEE 1687 Networks. - Farrokh Ghani Zadegan; Dimitar Nikolov; Erik Larsson (IEEE Trans. Computers, 2018)

IEEE Std. P1687.1: Translator and Protocol. - Erik Larsson; Prathamesh Murali; Gani Kumisbek (ITC, 2019)

Test Flow Selection for Stacked Integrated Circuits. - Breeta SenGupta; Dimitar Nikolov; Assmitra Dash; Erik Larsson (J. Electron. Test., 2019)

IEEE Std. P1687.1 for Access Control of Reconfigurable Scan Networks. - Erik Larsson; Zehang Xiang; Prathamesh Murali (ETS, 2020)

Enabling Image Recognition on Constrained Devices Using Neural Network Pruning and a CycleGAN. - August Lidfeldt; Daniel Isaksson; Ludwig Hedlund; Simon Åberg; Markus Borg; Erik Larsson (IOT Companion, 2020)

Analyses of non-coding somatic drivers in 2,658 cancer whole genomes. - Esther Rheinbay; Morten Muhlig Nielsen; Federico Abascal; Jeremiah Wala; Ofer Shapira; Grace Tiao; Henrik Hornshøj; Julian M. Hess; Randi Istrup Juul; Ziao Lin; Lars Feuerbach; Radhakrishnan Sabarinathan; et al. (Nat., 2020)

System-Level Access to On-Chip Instruments. - Erik Larsson; Shashi Kiran Gangaraju; Prathamesh Murali (ETS, 2021)

Accessing general IEEE Std. 1687 networks via functional ports. - Erik Larsson; Prathamesh Murali; Ziling Zhang (ITC, 2021)

Graceful Degradation of Reconfigurable Scan Networks. - Erik Larsson; Zehang Xiang; Prathamesh Murali (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus. - Farrokh Ghani Zadegan; Zilin Zhang; Kim Petersén; Erik Larsson (ITC, 2022)

Co-optimization of security and accessibility to on-chip instruments. - Erik Larsson (LATS, 2023)

Embedded Tutorial: Access to On-chip Instruments via Functional Ports. - Erik Larsson (LATS, 2024)

Improving Relational Database Interactions with Large Language Models: Column Descriptions and Their Impact on Text-to-SQL Performance. - Niklas Wretblad; Oskar Holmström; Erik Larsson; Axel Wiksäter; Oscar Söderlund; Hjalmar Öhman; Ture Pontén; Martin Forsberg; Martin Sörme; Fredrik Heintz (CoRR, 2024)

On Modeling and Detecting Trojans in Instruction Sets. - Ying Zhang 040; Aodi He; Jiaying Li; Ahmed Rezine; Zebo Peng; Erik Larsson; Tao Yang; Jianhui Jiang; Huawei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Securing Reconfigurable Scan Networks Against Data Sniffing and Data Alteration Attacks. - Joel Åhlund; Markus Törmänen; Mikael Kerttu; Pamela Svensson; Torbjörn Månefjord; Christian Johansson; Erik Larsson (ETS, 2025)

Securing the Control of Digital Beamforming. - Love Barany; William Eriksson; Joel Åhlund; Daniel Bakic; Erik Larsson; Joakim Axmon; Markus Törmänen (IOLTS, 2025)

Large Language Models for Printed Circuit Board Test Generation. - Albin Lidbäck; Erik Larsson (LATS, 2025)

Diffusion-LAM: Probabilistic Limited Area Weather Forecasting with Diffusion. - Erik Larsson; Joel Oskarsson; Tomas Landelius; Fredrik Lindsten (CoRR, 2025)