Analog Design for a Power Transmission Line Sensing and Analysis VLSI Chip. - Erik MacLean; Vijay K. Jain (DFT, 2010)

A Power Transmission Line Fault Distance Estimation VLSI Chip: Design and Defect Tolerance. - Erik MacLean; Vijay K. Jain (DFT, 2011)

Hardware and Energy Efficiency Evaluation of NIST Lightweight Cryptography Standardization Finalists. - Islam Elsadek; Sohrab Aftabjahani; Doug Gardner; Erik MacLean; John Ross Wallrabenstein; Eslam Yahya Tawfik (ISCAS, 2022)

Energy Efficiency Enhancement Of Parallelized Implementation of NIST Lightweight Cryptography Standardization Finalists. - Islam Elsadek; Sohrab Aftabjahani; Doug Gardner; Erik MacLean; John Ross Wallrabenstein; Eslam Yahya Tawfik (ISCAS, 2022)

State-of-the-Art ASCON ASIC Achieving 4.3 Gbps@0.8V and 3.5Tb/J@0.6V Outperforming AES by 25 Times. - Islam Elsadek; Elsayed Elgendy; Sherif Abouzeid; Ahmed Zaky Ghonem; John Ross Wallrabenstein; Erik MacLean; Douglas Gardner; Sohrab Aftabjahani; Rosario Cammarota; Eslam Yahya Tawfik (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)