A 1.8 V 10-bit 80 MS/s low power track-and-hold circuit in a 0.18µm CMOS process. - Erik Säll (ISCAS (1), 2003)

A study of digital decoders in flash analog-to-digital converters. - Erik Säll; Mark Vesterbacka; K. Ola Andersson (ISCAS (1), 2004)

Design of a Comparator in CMOS SOI. - Erik Säll; Mark Vesterbacka (IWSOC, 2004)

6 bit 1 GHz CMOS silicon-on-insulator flash analog-to-digital converter for read channel applications. - Erik Säll; Mark Vesterbacka (ECCTD, 2005)

Bidirectional conversion to minimum signed-digit representation. - Erik Backenius; Erik Säll; Oscar Gustafsson (ISCAS, 2006)

Thermometer-to-binary decoders for flash analog-to-digital converters. - Erik Säll; Mark Vesterbacka (ECCTD, 2007)

A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology. - Staffan Ek; Patrik Karlsson; Andreas Kämpe; Roland Strandberg; Aravind Tharayil Narayanan; Martin Anderson; Hind Dafallah; Mesrop Daghbashyan; Tayebeh Ghanavati Nejad; Robert Hägglund; Nikola Ivanisevic; Robert Nilsson; et al. (ESSCIRC, 2022)

A 12/16 GSps Time-Interleaved Pipelined-SAR ADC with Temperature Robust Performance at 0.75V Supply in 7nm FinFET Technology. - Mattias Palm; Daniele Mastantuono; Christer Jansson; Erik Backenius; Nikola Ivanisevic; Mikael Normark; Prakash Harikumar; My-Chien Yee; Andreas Leidenhed; Roland Strandberg; Sunny Sharma; Hanie Ghaedrahmati; et al. (ESSCIRC, 2023)