A Comparative Study of Dynamic Voltage Scaling Techniques for Low-Power Video Decoding. - Eriko Nurvitadhi; Ben Lee; Chansu Yu; Myungchul Kim 001 (Embedded Systems and Applications, 2003)

Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C. - Eriko Nurvitadhi; Nirut Chalainanont; Shih-Lien Lu (ICS, 2005)

Dynamic voltage scaling techniques for power efficient video decoding. - Ben Lee; Eriko Nurvitadhi; Reshma Dixit; Chansu Yu; Myungchul Kim 001 (J. Syst. Archit., 2005)

TRUSS: A Reliable, Scalable Server Architecture. - Brian T. Gold; Jangwoo Kim; Jared C. Smolens; Eric S. Chung; Vasileios Liaskovitis; Eriko Nurvitadhi; Babak Falsafi; James C. Hoe; Andreas Nowatzyk (IEEE Micro, 2005)

Design, implementation, and verification of active cache emulator (ACE). - Jumnit Hong; Eriko Nurvitadhi; Shih-Lien Lu (FPGA, 2006)

PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. - Eric S. Chung; Eriko Nurvitadhi; James C. Hoe; Babak Falsafi; Ken Mai (IPDPS, 2007)

Adaptive semi-soft handoff for Cellular IP networks. - Eriko Nurvitadhi; Ben Lee; Chansu Yu; Myungchul Kim 001 (Int. J. Wirel. Mob. Comput., 2007)

A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. - Eric S. Chung; Eriko Nurvitadhi; James C. Hoe; Babak Falsafi; Ken Mai (FPGA, 2008)

Active Cache Emulator. - Eriko Nurvitadhi; Jumnit Hong; Shih-Lien Lu (IEEE Trans. Very Large Scale Integr. Syst., 2008)

ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. - Eric S. Chung; Michael Papamichael; Eriko Nurvitadhi; James C. Hoe; Ken Mai; Babak Falsafi (ACM Trans. Reconfigurable Technol. Syst., 2009)

Automatic multithreaded pipeline synthesis from transactional datapath specifications. - Eriko Nurvitadhi; James C. Hoe; Shih-Lien Lu; Timothy Kam (DAC, 2010)

Integrating formal verification and high-level processor pipeline synthesis. - Eriko Nurvitadhi; James C. Hoe; Timothy Kam; Shih-Lien Lu (SASP, 2011)

Automatic Pipelining From Transactional Datapath Specifications. - Eriko Nurvitadhi; James C. Hoe; Timothy Kam; Shih-Lien Lu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming. - Hyun Soo Park; Yu Wang 110; Eriko Nurvitadhi; James C. Hoe; Yaser Sheikh; Mei Chen (CVPR Workshops, 2013)

Hardware-efficient stereo estimation using a residual-based approach. - Abhishek A. Sharma; Kaustubh Neelathalli; Diana Marculescu; Eriko Nurvitadhi (ICASSP, 2013)

MEMOCODE 2013 hardware/software co-design contest: Stereo matching. - Eriko Nurvitadhi (MEMOCODE, 2013)

Programmable Automotive Headlights. - Robert Tamburo; Eriko Nurvitadhi; Abhishek Chugh; Mei Chen; Anthony Rowe 001; Takeo Kanade; Srinivasa G. Narasimhan (ECCV (4), 2014)

GraphGen: An FPGA Framework for Vertex-Centric Graph Computation. - Eriko Nurvitadhi; Gabriel Weisz; Yu Wang 110; Skand Hurkat; Marie Nguyen; James C. Hoe; José F. Martínez; Carlos Guestrin (FCCM, 2014)

A sparse matrix vector multiply accelerator for support vector machine. - Eriko Nurvitadhi; Asit K. Mishra; Debbie Marr (CASES, 2015)

Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference. - Skand Hurkat; Jungwook Choi; Eriko Nurvitadhi; José F. Martínez; Rob A. Rutenbar (FPL, 2015)

Hardware accelerator for analytics of sparse data. - Eriko Nurvitadhi; Asit K. Mishra; Yu Wang 110; Ganesh Venkatesh; Debbie Marr (DATE, 2016)

A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems. - Gabriel Weisz; Joseph Melber; Yu Wang 110; Kermin Fleming; Eriko Nurvitadhi; James C. Hoe (FPGA, 2016)

Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC. - Eriko Nurvitadhi; Jaewoong Sim; David Sheffield; Asit K. Mishra; Krishnan Srivatsan; Debbie Marr (FPL, 2016)

Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC. - Eriko Nurvitadhi; David Sheffield; Jaewoong Sim; Asit K. Mishra; Ganesh Venkatesh; Debbie Marr (FPT, 2016)

3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming. - Hyun Soo Park; Yu Wang 110; Eriko Nurvitadhi; James C. Hoe; Yaser Sheikh; Mei Chen (Large-Scale Visual Geo-Localization, 2016)

Fine-grained accelerators for sparse machine learning workloads. - Asit K. Mishra; Eriko Nurvitadhi; Ganesh Venkatesh; Jonathan Pearce; Debbie Marr (ASP-DAC, 2017)

Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks? - Eriko Nurvitadhi; Ganesh Venkatesh; Jaewoong Sim; Debbie Marr; Randy Huang; Jason Ong Gee Hock; Yeong Tat Liew; Krishnan Srivatsan; Duncan J. M. Moss; Suchit Subhaschandra; Guy Boudoukh (FPGA, 2017)

High performance binary neural networks on the Xeon+FPGA™ platform. - Duncan J. M. Moss; Eriko Nurvitadhi; Jaewoong Sim; Asit K. Mishra; Debbie Marr; Suchit Subhaschandra; Philip Heng Wai Leong (FPL, 2017)

Customizable FPGA OpenCL matrix multiply design template for deep neural networks. - Jack Yinger; Eriko Nurvitadhi; Davor Capalija; Andrew C. Ling; Debbie Marr; Krishnan Srivatsan; Duncan J. M. Moss; Suchit Subhaschandra (FPT, 2017)

Accelerating Deep Convolutional Networks using low-precision and sparsity. - Ganesh Venkatesh; Eriko Nurvitadhi; Debbie Marr (ICASSP, 2017)

WRPN: Training and Inference using Wide Reduced-Precision Networks. - Asit K. Mishra; Jeffrey J. Cook; Eriko Nurvitadhi; Debbie Marr (CoRR, 2017)

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs. - Philip Colangelo; Nasibeh Nasiri; Eriko Nurvitadhi; Asit K. Mishra; Martin Margala; Kevin Nealis (FCCM, 2018)

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only). - Philip Colangelo; Nasibeh Nasiri; Eriko Nurvitadhi; Asit K. Mishra; Martin Margala; Kevin Nealis (FPGA, 2018)

A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study. - Duncan J. M. Moss; Krishnan Srivatsan; Eriko Nurvitadhi; Piotr Ratuszniak; Chris Johnson; Jaewoong Sim; Asit K. Mishra; Debbie Marr; Suchit Subhaschandra; Philip Heng Wai Leong (FPGA, 2018)

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). - Eriko Nurvitadhi; Jeffrey J. Cook; Asit K. Mishra; Debbie Marr; Kevin Nealis; Philip Colangelo; Andrew C. Ling; Davor Capalija; Utku Aydonat; Sergey Y. Shumarayev; Aravind Dasu (FPGA, 2018)

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. - Eriko Nurvitadhi; Jeffrey J. Cook; Asit K. Mishra; Debbie Marr; Kevin Nealis; Philip Colangelo; Andrew C. Ling; Davor Capalija; Utku Aydonat; Aravind Dasu; Sergey Y. Shumarayev (FPL, 2018)

Evaluating The Highly-Pipelined Intel Stratix 10 FPGA Architecture Using Open-Source Benchmarks. - Tian Tan 007; Eriko Nurvitadhi; David Shih; Derek Chiou (FPT, 2018)

WRPN: Wide Reduced-Precision Networks. - Asit K. Mishra; Eriko Nurvitadhi; Jeffrey J. Cook; Debbie Marr (ICLR (Poster), 2018)

Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs. - Philip Colangelo; Nasibeh Nasiri; Asit K. Mishra; Eriko Nurvitadhi; Martin Margala; Kevin Nealis (CoRR, 2018)

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. - Eriko Nurvitadhi; Dongup Kwon; Ali Jafari; Andrew Boutros; Jaewoong Sim; Phillip Tomson; Huseyin Sumbul; Gregory K. Chen; Phil C. Knag; Raghavan Kumar; Ram Krishnamurthy 001; Sergey Gribok; et al. (FCCM, 2019)

Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory Platform. - Yu Wang 110; James C. Hoe; Eriko Nurvitadhi (FCCM, 2019)

Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. - Eriko Nurvitadhi; Dongup Kwon; Ali Jafari; Andrew Boutros; Jaewoong Sim; Phillip Tomson; Huseyin Sumbul; Gregory K. Chen; Phil C. Knag; Raghavan Kumar; Ram Krishnamurthy 001; Debbie Marr; et al. (FPGA, 2019)

Automatic Compiler Based FPGA Accelerator for CNN Training. - Shreyas Kolala Venkataramanaiah; Yufei Ma 002; Shihui Yin; Eriko Nurvitadhi; Aravind Dasu; Yu Cao 001; Jae-sun Seo (FPL, 2019)

Scalable Low-Latency Persistent Neural Machine Translation on CPU Server with Multiple FPGAs. - Eriko Nurvitadhi; Mishali Naik; Andrew Boutros; Prerna Budhkar; Ali Jafari; Dongup Kwon; David Sheffield; Abirami Prabhakaran; Karthik Gururaj; Pranavi Appana (FPT, 2019)

Enhanced Heterogeneous Cloud: Transparent Acceleration and Elasticity. - Jessica Vandebon; José Gabriel F. Coutinho; Wayne Luk; Eriko Nurvitadhi; Mishali Naik (FPT, 2019)

FPGA-based Computing in the Era of AI and Big Data. - Eriko Nurvitadhi (ISPD, 2019)

Dark Wires and the Opportunities for Reconfigurable Logic. - Tian Tan 007; Eriko Nurvitadhi; Derek Chiou (IEEE Comput. Archit. Lett., 2019)

SLATE: Managing Heterogeneous Cloud Functions. - Jessica Vandebon; José Gabriel F. Coutinho; Wayne Luk; Eriko Nurvitadhi; Mishali Naik (ASAP, 2020)

Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism Levels. - Dongup Kwon; Suyeon Hur; Hamin Jang; Eriko Nurvitadhi; Jangwoo Kim (DAC, 2020)

Optimizing Reconfigurable Recurrent Neural Networks. - Zhiqiang Que; Hiroki Nakahara; Eriko Nurvitadhi; Hongxiang Fan; Chenglong Zeng; Jiuxi Meng; Xinyu Niu; Wayne Luk (FCCM, 2020)

Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies. - Jessica Vandebon; José Gabriel F. Coutinho; Wayne Luk; Eriko Nurvitadhi; Tim Todman (FCCM, 2020)

FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. - Shreyas K. Venkataramanaiah; Han-Sok Suh; Shihui Yin; Eriko Nurvitadhi; Aravind Dasu; Yu Cao 001; Jae-Sun Seo (ICCAD, 2020)

Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUs. - Andrew Boutros; Eriko Nurvitadhi; Rui Ma; Sergey Gribok; Zhipeng Zhao; James C. Hoe; Vaughn Betz; Martin Langhammer (FPT, 2020)

A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. - Zhiqiang Que; Hiroki Nakahara; Hongxiang Fan; Jiuxi Meng; Kuen Hung Tsoi; Xinyu Niu; Eriko Nurvitadhi; Wayne Luk (FPT, 2020)

Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. - Xiaowei Wang; Vidushi Goyal; Jiecao Yu; Valeria Bertacco; Andrew Boutros; Eriko Nurvitadhi; Charles Augustine; Ravi R. Iyer 001; Reetuparna Das (FCCM, 2021)

Stratix 10 NX Architecture and Applications. - Martin Langhammer; Eriko Nurvitadhi; Bogdan Pasca 001; Sergey Gribok (FPGA, 2021)

End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. - Anupreetham Anupreetham; Mohamed Ibrahim; Mathew Hall; Andrew Boutros; Ajay Kuzhively; Abinash Mohanty; Eriko Nurvitadhi; Vaughn Betz; Yu Cao 001; Jae-sun Seo (FPL, 2021)

DO-GPU: Domain Optimizable Soft GPUs. - Rui Ma; Jia-Ching Hsu; Tian Tan 007; Eriko Nurvitadhi; Rajesh Vivekanandham; Aravind Dasu; Martin Langhammer; Derek Chiou (FPL, 2021)

Specializing for Efficiency: Customizing AI Inference Processors on FPGAs. - Andrew Boutros; Eriko Nurvitadhi; Vaughn Betz (ICM, 2021)

Cache Compression with Efficient in-SRAM Data Comparison. - Xiaowei Wang; Charles Augustine; Eriko Nurvitadhi; Ravi R. Iyer 001; Li Zhao 002; Reetuparna Das (NAS, 2021)

FlexScore: Quantifying Flexibility. - Tian Tan 007; Eriko Nurvitadhi; Aravind Dasu; Martin Langhammer; Derek Chiou (IEEE Comput. Archit. Lett., 2021)

Enhancing High-Level Synthesis Using a Meta-Programming Approach. - Jessica Vandebon; José Gabriel de Figueiredo Coutinho; Wayne Luk; Eriko Nurvitadhi (IEEE Trans. Computers, 2021)

Specializing FGPU for Persistent Deep Learning. - Rui Ma; Jia-Ching Hsu; Tian Tan 007; Eriko Nurvitadhi; David Sheffield; Rob Pelt; Martin Langhammer; Jaewoong Sim; Aravind Dasu; Derek Chiou (ACM Trans. Reconfigurable Technol. Syst., 2021)

HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming. - Adel Ejjeh; Leon Medvinsky; Aaron Councilman; Hemang Nehra; Suraj Sharma; Vikram S. Adve; Luigi Nardi; Eriko Nurvitadhi; Rob A. Rutenbar (ASAP, 2022)

RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices. - Andrew Boutros; Eriko Nurvitadhi; Vaughn Betz (FPL, 2022)

Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices. - Andrew Boutros; Eriko Nurvitadhi; Vaughn Betz (IEEE Access, 2022)

FPGA-Based AI Smart NICs for Scalable Distributed AI Training Systems. - Rui Ma; Evangelos Georganas; Alexander Heinecke; Sergey Gribok; Andrew Boutros; Eriko Nurvitadhi (IEEE Comput. Archit. Lett., 2022)

FPGA-based AI Smart NICs for Scalable Distributed AI Training Systems. - Rui Ma; Evangelos Georganas; Alexander Heinecke; Andrew Boutros; Eriko Nurvitadhi (CoRR, 2022)

Stratix 10 NX Architecture. - Martin Langhammer; Eriko Nurvitadhi; Sergey Gribok; Bogdan Pasca 001 (ACM Trans. Reconfigurable Technol. Syst., 2022)

Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. - Zhiqiang Que; Hiroki Nakahara; Eriko Nurvitadhi; Andrew Boutros; Hongxiang Fan; Chenglong Zeng; Jiuxi Meng; Kuen Hung Tsoi; Xinyu Niu; Wayne Luk (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks. - Suyeon Hur; Seongmin Na; Dongup Kwon; Joonsung Kim; Andrew Boutros; Eriko Nurvitadhi; Jangwoo Kim (ACM Trans. Archit. Code Optim., 2023)

Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. - Zhiqiang Que; Hiroki Nakahara; Hongxiang Fan; He Li 008; Jiuxi Meng; Kuen Hung Tsoi; Xinyu Niu; Eriko Nurvitadhi; Wayne Luk (ACM Trans. Reconfigurable Technol. Syst., 2023)

Exploiting the Common Case When Accelerating Input-Dependent Stream Processing by FPGA. - Zhipeng Zhao; Joseph Melber; Siddharth Sahay; Shashank Obla; Eriko Nurvitadhi; James C. Hoe (IEEE Trans. Computers, 2023)

High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design. - Anupreetham Anupreetham; Mohamed Ibrahim; Mathew Hall; Andrew Boutros; Ajay Kuzhively; Abinash Mohanty; Eriko Nurvitadhi; Vaughn Betz; Yu Cao 001; Jae-Sun Seo (ACM Trans. Reconfigurable Technol. Syst., 2024)

FLASH: Fast All-to-All Communication in GPU Clusters. - Yiran Lei; Dongjoo Lee; Liangyu Zhao; Daniar Kurniawan; Chanmyeong Kim; Heetaek Jeong; Changsu Kim 004; Hyeonseong Choi; Liangcheng Yu; Arvind Krishnamurthy; Justine Sherry; Eriko Nurvitadhi (CoRR, 2025)