Single-row routing and extensions. - Ernest S. Kuh (COMPSAC, 1979)

One-dimensional logic gate assignment and interval graphs. - Tatsuo Ohtsuki; Hajimu Mori; Ernest S. Kuh; Toshinobu Kashiwabara; Toshio Fujisawa (COMPSAC, 1979)

Double-row planar routing and permutation layout. - Shuji Tsukiyama; Ernest S. Kuh (Networks, 1982)

Efficient Algorithms for Channel Routing. - Takeshi Yoshimura; Ernest S. Kuh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1982)

Editorial: Routing in Microelectronics. - Ernest S. Kuh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

On the Layering Problem of Multilayer PWB Wiring. - Shuji Tsukiyama; Ernest S. Kuh; Isao Shirakawa (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

Module Placement Based on Resistive Network Optimization. - Chung-Kuan Cheng; Ernest S. Kuh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

An Efficient Single-Row Routing Algorithm. - Tom Tsan-Kuo Tarng; Malgorzata Marek-Sadowska; Ernest S. Kuh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

Routing Region Definition and Ordering Scheme for Building-Block Layout. - Wayne Wei-Ming Dai; Tetsuo Asano; Ernest S. Kuh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985)

Glitter: A Gridless Variable-Width Channel Router. - Howard H. Chen; Ernest S. Kuh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

A Dynamic and Efficient Representation of Building-Block Layout. - Wayne Wei-Ming Dai; Masao Sato; Ernest S. Kuh (DAC, 1987)

Nutcracker: An Efficient and Intelligent Channel Spacer. - Xiao-Ming Xiong; Ernest S. Kuh (DAC, 1987)

Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout. - Wayne Wei-Ming Dai; Ernest S. Kuh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Proud: A Fast Sea-of-Gates Placement Algorithm. - Ren-Song Tsay; Ernest S. Kuh; Chi-Ping Hsu (DAC, 1988)

The Constrained Via Minimization Problem for PCB and VLSI Design. - Xiao-Ming Xiong; Ernest S. Kuh (DAC, 1988)

A sequential circuit test generation using threshold-value simulation. - Kwang-Ting Cheng; Vishwani D. Agrawal; Ernest S. Kuh (FTCS, 1988)

Hierarchical placement for macrocells: a 'meet in the middle' approach. - Bernhard Eschermann; Wayne Wei-Ming Dai; Ernest S. Kuh; Massoud Pedram (ICCAD, 1988)

PROUD: a sea-of-gates placement algorithm. - Ren-Song Tsay; Ernest S. Kuh; Chi-Ping Hsu (IEEE Des. Test, 1988)

Performance-driven Placement of Cell Based IC's. - Michael A. B. Jackson; Ernest S. Kuh (DAC, 1989)

Clock Routing for High-Performance ICs. - Michael A. B. Jackson; Arvind Srinivasan 004; Ernest S. Kuh (DAC, 1990)

Delay and Area Optimization in Standard-Cell Design. - Shen Lin 001; Malgorzata Marek-Sadowska; Ernest S. Kuh (DAC, 1990)

MOLE: a sea-of-gates detailed router. - Arvind Srinivasan 004; Ernest S. Kuh (EURO-DAC, 1990)

A Fast Algorithm for Performance-Driven Placement. - Michael A. B. Jackson; Arvind Srinivasan 004; Ernest S. Kuh (ICCAD, 1990)

Floorplanning with Pin Assignment. - Massoud Pedram; Malgorzata Marek-Sadowska; Ernest S. Kuh (ICCAD, 1990)

Geometric approach to VLSI layout compaction. - Xiao-Ming Xiong; Ernest S. Kuh (Int. J. Circuit Theory Appl., 1990)

Recent advances in VLSI layout. - Ernest S. Kuh; Tatsuo Ohtsuki (Proc. IEEE, 1990)

A Simulation-Based Method for Generating Tests for Sequential Circuits. - Kwang-Ting Cheng; Vishwani D. Agrawal; Ernest S. Kuh (IEEE Trans. Computers, 1990)

SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits. - Shen Lin 001; Malgorzata Marek-Sadowska; Ernest S. Kuh (EURO-DAC, 1991)

RITUAL: Performance Driven Placement Algorithm for Small Cell ICs. - Arvind Srinivasan 004; Kamal Chaudhary; Ernest S. Kuh (ICCAD, 1991)

I/O Pad Assignment Based on the Circuit Structure. - Massoud Pedram; Kamal Chaudhary; Ernest S. Kuh (ICCD, 1991)

New Algorithms For Two- and Three-Layer Channel Routin. - Deborah C. Wang; Ernest S. Kuh (Int. J. Circuit Theory Appl., 1991)

FARM: An Efficient Feed-Through Pin Assignment Algorithm. - Xianlong Hong; Jin Huang; Chung-Kuan Cheng; Ernest S. Kuh (DAC, 1992)

Transient Simulation of Lossy Interconnect. - Shen Lin 001; Ernest S. Kuh (DAC, 1992)

Power and Ground Network Topology Optimization for Cell Based VLSIs. - Takashi Mitsuhashi; Ernest S. Kuh (DAC, 1992)

Performance-Driven System Partitioning on Multi-Chip Modules. - Minshine Shih; Ernest S. Kuh; Ren-Song Tsay (DAC, 1992)

Transient simulation of lossy coupled transmission lines. - Shen Lin 001; Ernest S. Kuh (EURO-DAC, 1992)

A New Accurate and Efficient Timing Simulator. - Shen Lin 001; Ernest S. Kuh; Malgorzata Marek-Sadowska (VLSI Design, 1992)

Performance-Driven Steiner Tree Algorithm for Global Routing. - Xianlong Hong; Tianxiong Xue; Ernest S. Kuh; Chung-Kuan Cheng; Jin Huang (DAC, 1993)

An Efficient Timing-Driven Global Routing Algorithm. - Jin Huang; Xianlong Hong; Chung-Kuan Cheng; Ernest S. Kuh (DAC, 1993)

Quadratic Boolean Programming for Performance-Driven System Partitioning. - Minshine Shih; Ernest S. Kuh (DAC, 1993)

A spacing algorithm for performance enhancement and cross-talk reduction. - Kamal Chaudhary; Akira Onozawa; Ernest S. Kuh (ICCAD, 1993)

Circuit simulation for large interconnected IC networks. - Shen Lin 001; Ernest S. Kuh (VLSI, 1993)

A new performance-driven global routing algorithm for gate array. - Tianxiong Xue; Takashi Fujii; Ernest S. Kuh (VLSI, 1993)

Stepwise equivalent conductance circuit simulation technique. - Shen Lin 001; Ernest S. Kuh; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Post routing performance optimization via tapered link insertion and wiresizing. - Tianxiong Xue; Ernest S. Kuh (EURO-DAC, 1995)

Post routing performance optimization via multi-link insertion and non-uniform wiresizing. - Tianxiong Xue; Ernest S. Kuh (ICCAD, 1995)

Techniques for fast circuit simulation applied to power estimation of CMOS circuits. - Premal Buch; Shen Lin 001; Vijay Nagasamy; Ernest S. Kuh (ISLPD, 1995)

Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's. - Akira Onozawa; Kamal Chaudhary; Ernest S. Kuh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Exact moment matching model of transmission lines and application to interconnect delay estimation. - Qingjian Yu; Ernest S. Kuh (IEEE Trans. Very Large Scale Integr. Syst., 1995)

EXPLORER: an interactive floorplanner for design space exploration. - Henrik Esbensen; Ernest S. Kuh (EURO-DAC, 1996)

Performance-Driven Interconnect Global Routing. - Dongsheng Wang 012; Ernest S. Kuh (Great Lakes Symposium on VLSI, 1996)

Simulation and sensitivity analysis of transmission line circuits by the characteristics method. - Jun-Fa Mao; Janet Meiling Wang; Ernest S. Kuh (ICCAD, 1996)

Post global routing crosstalk risk estimation and reduction. - Tianxiong Xue; Ernest S. Kuh; Dongsheng Wang 012 (ICCAD, 1996)

Moment models of general transmission lines with application to interconnect analysis and optimization. - Qingjian Yu; Ernest S. Kuh; Tianxiong Xue (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Physical design: reminiscing and looking ahead. - Ernest S. Kuh (ISPD, 1997)

SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits. - Premal Buch; Ernest S. Kuh (VLSI Design, 1997)

TIGER: an efficient timing-driven global router for gate array and standard cell layout design. - Xianlong Hong; Tianxiong Xue; Jin Huang; Chung-Kuan Cheng; Ernest S. Kuh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Post global routing crosstalk synthesis. - Tianxiong Xue; Ernest S. Kuh; Dongsheng Wang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

A performance-driven IC/MCM placement algorithm featuring explicit design space exploration. - Henrik Esbensen; Ernest S. Kuh (ACM Trans. Design Autom. Electr. Syst., 1997)

Combining Technology Mapping With Layout. - Massoud Pedram; Narasimha B. Bhat; Ernest S. Kuh (VLSI Design, 1997)

A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction. - Dongsheng Wang 012; Ernest S. Kuh (DATE, 1998)

Multipoint moment matching model for multiport distributed interconnect networks. - Qingjian Yu; Janet Meiling Wang; Ernest S. Kuh (ICCAD, 1998)

A new general connectivity model and its applications to timing-driven Steiner tree routing. - Dongsheng Wang 012; Ernest S. Kuh (ICECS, 1998)

Sequence-pair based placement method for hard/soft/pre-placed modules. - Hiroshi Murata; Ernest S. Kuh (ISPD, 1998)

Coupled Noise Estimation for Distributed RC Interconnect Model. - Janet Meiling Wang; Qingjian Yu; Ernest S. Kuh (DATE, 1999)

The Chebyshev expansion based passive model for distributed interconnect networks. - Janet Meiling Wang; Ernest S. Kuh; Qingjian Yu (ICCAD, 1999)

Floorplan sizing by linear programming approximation. - Pinghong Chen; Ernest S. Kuh (DAC, 2000)

Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks. - Qingjian Yu; Janet Meiling Wang; Ernest S. Kuh (DAC, 2000)

Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements. - Qingjian Yu; Ernest S. Kuh (DATE, 2001)

New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees. - Qingjian Yu; Ernest S. Kuh (ISQED, 2001)

Moment computation of lumped and distributed coupled RC trees with application to delay and crosstalk estimation. - Qingjian Yu; Ernest S. Kuh (Proc. IEEE, 2001)

Accurate reduced RL model for frequency dependent transmission lines. - Qingjian Yu; Ernest S. Kuh (ICECS, 2002)

Efficient transient simulation for transistor-level analysis. - Zhengyong Zhu; Khosro Rouz; Manjit Borah; Chung-Kuan Cheng; Ernest S. Kuh (ASP-DAC, 2005)

An unconditional stable general operator splitting method for transistor level transient analysis. - Zhengyong Zhu; Rui Shi 003; Chung-Kuan Cheng; Ernest S. Kuh (ASP-DAC, 2006)

Two-Stage Newton-Raphson Method for Transistor-Level Simulation. - Zhengyong Zhu; He Peng; Chung-Kuan Cheng; Khosro Rouz; Manjit Borah; Ernest S. Kuh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Low power passive equalizer optimization using tritonic step response. - Ling Zhang; Wenjian Yu; Haikun Zhu; Alina Deutsch; George A. Katopis; Daniel M. Dreps; Ernest S. Kuh; Chung-Kuan Cheng (DAC, 2008)

Low Power Passive Equalizer Design for Computer Memory Links. - Ling Zhang; Wenjian Yu; Yulei Zhang 002; Renshen Wang; Alina Deutsch; George A. Katopis; Daniel M. Dreps; James F. Buckwalter; Ernest S. Kuh; Chung-Kuan Cheng (Hot Interconnects, 2008)

Efficient and accurate eye diagram prediction for high speed signaling. - Rui Shi 003; Wenjian Yu; Yi Zhu 002; Chung-Kuan Cheng; Ernest S. Kuh (ICCAD, 2008)

High performance on-chip differential signaling using passive compensation for global communication. - Ling Zhang; Yulei Zhang 002; Akira Tsuchiya; Masanori Hashimoto; Ernest S. Kuh; Chung-Kuan Cheng (ASP-DAC, 2009)

Design methodology of high performance on-chip global interconnect using terminated transmission-line. - Yulei Zhang 002; Ling Zhang; Alina Deutsch; George A. Katopis; Daniel M. Dreps; James F. Buckwalter; Ernest S. Kuh; Chung-Kuan Cheng (ISQED, 2009)

Professor Ernest Kuh's talk. - Ernest S. Kuh (ISPD, 2011)