Super-audio CD: an introduction. - Erwin Janssen; Derk Reefman (IEEE Signal Process. Mag., 2003)

Lossless compression of one-bit audio. - Erwin Janssen; Eric Knapen; Derk Reefman; Fons Bruekers (ICASSP (3), 2004)

Description of limit cycles in sigma-delta modulators. - Derk Reefman; Joshua D. Reiss; Erwin Janssen; Mark B. Sandler (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist. - Konstantinos Doris; Erwin Janssen; Claudio Nani; Athon Zanikopoulos; Gerard van der Weide (ISSCC, 2011)

A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS. - Kostas Doris; Erwin Janssen; Claudio Nani; Athon Zanikopoulos; Gerard van der Weide (IEEE J. Solid State Circuits, 2011)

An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals. - Yu Lin 003; Kostas Doris; Erwin Janssen; Athon Zanikopoulos; Alessandro Murroni; Gerard van der Weide; Hans Hegt; Arthur H. M. van Roermund (ESSCIRC, 2013)

An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS. - Erwin Janssen; Kostas Doris; Athon Zanikopoulos; Alessandro Murroni; Gerard van der Weide; Yu Lin 003; Ludo Alvado; Frederic Darthenay; Yannick Fregeais (ISSCC, 2013)

15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS. - Martin Kramer; Erwin Janssen; Kostas Doris; Boris Murmann (ISSCC, 2015)

A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS. - Martin Kramer; Erwin Janssen; Kostas Doris; Boris Murmann (IEEE J. Solid State Circuits, 2015)

A 14-Bit 30-MS/s 38-mW SAR ADC Using Noise Filter Gear Shifting. - Martin Kramer; Erwin Janssen; Kostas Doris; Boris Murmann (IEEE Trans. Circuits Syst. II Express Briefs, 2017)