Two-dimensional IC layout compaction based on topological design rule checking. - John Valainis; Sinan Kaptanoglu; Erwin Liu; Roberto Suaya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

From formal verification to silicon compilation. - Jeffrey Joyce; Erwin Liu; John M. Rushby; Natarajan Shankar; Roberto Suaya; Friedrich W. von Henke (Compcon, 1991)

A Two-Dimensional Topological Compactor With Octagonal Geometry. - Paul de Dood; John Wawrzynek; Erwin Liu; Roberto Suaya (DAC, 1991)