Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA. - François Charot; Eslam Yahya; Charles Wagner (FPL, 2003)

QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. - Eslam Yahya; Marc Renaudin (PATMOS, 2006)

Performance Modeling and Analysis of Asynchronous Linear-Pipeline with Time Variable Delays. - Eslam Yahya; Marc Renaudin (ICECS, 2007)

Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm. - Eslam Yahya; Marc Renaudin (ICECS, 2008)

Programmable/Stoppable Oscillator Based on Self-Timed Rings. - Eslam Yahya; Oussama Elissati; Hatem Zakaria; Laurent Fesquet; Marc Renaudin (ASYNC, 2009)

Asynchronous design: A promising paradigm for electronic circuits and systems. - Eslam Yahya; Laurent Fesquet (ICECS, 2009)

Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case. - Oussama Elissati; Eslam Yahya; Sébastien Rieubon; Laurent Fesquet (PATMOS, 2010)

Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks. - Oussama Elissati; Sébastien Rieubon; Eslam Yahya; Laurent Fesquet (VLSI-SoC (Selected Papers), 2010)

A high-speed high-resolution low-phase noise oscillator using self-timed rings. - Oussama Elissati; Eslam Yahya; Sébastien Rieubon; Laurent Fesquet (VLSI-SoC, 2010)

Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. - Eslam Yahya; Laurent Fesquet; Yehea I. Ismail; Marc Renaudin (ASYNC, 2013)

Variability mitigation using correction function technique. - Shady O. Agwa; Eslam Yahya; Yehea I. Ismail (ICECS, 2013)

Different scenarios for estimating coupling capacitances of through silicon via (TSV) arrays. - Kareem Ali; Eslam Yahya; Alaa B. El-Rouby; Yehea Ismail (ICEAC, 2015)

Coupling capacitance extraction in through-silicon via (TSV) arrays. - Tarek Ramadan; Eslam Yahya; Mohamed Dessouky; Yehea I. Ismail (ICECS, 2015)

Deadlock detection in conditional asynchronous circuits under mismatched branch selection. - Eslam Yahya; Hatem Zakaria; Yehea Ismail (ICECS, 2015)

Library based macro-modeling methodology for Through Silicon Via (TSV) arbitrary arrays. - Karim Ali 003; Eslam Yahya; Alaa B. El-Rouby; Yehea I. Ismail (Microelectron. J., 2015)

Presenting a synchronous - Asynchronous standard cell library based on 7nm FinFET technology. - Eslam Amr; Marina Maher; Amir Rashad; Mohamed Raafat; Yosif Diaa; Eslam Yahya; Yehea Ismail (ICM, 2016)

Accuracy-improved coupling capacitance model for through-silicon via (TSV) arrays using dimensional analysis. - Tarek Ramadan; Eslam Yahya; Mohamed Dessouky; Yehea Ismail (ISCAS, 2016)

ERSUT: A Self-Healing Architecture for Mitigating PVT Variations Without Pipeline Flushing. - Shady O. Agwa; Eslam Yahya; Yehea Ismail (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Power efficient AES core for IoT constrained devices implemented in 130nm CMOS. - Shady O. Agwa; Eslam Yahya; Yehea Ismail (ISCAS, 2017)

130nm Low power asynchronous AES core. - Nada El-meligy; Moustafa Amin; Eslam Yahya; Yehea Ismail (ISCAS, 2017)

A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation. - Shady O. Agwa; Eslam Yahya; Yehea Ismail (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)