Balancing the Interconnect Topology for Arrays of Processors between Cost and Power. - Esther Y. Cheng; Feng Zhou; Bo Yao 004; Chung-Kuan Cheng; Ronald L. Graham (ICCD, 2002)

A hierarchical three-way interconnect architecture for hexagonal processors. - Feng Zhou; Esther Y. Cheng; Bo Yao 004; Chung-Kuan Cheng; Ronald L. Graham (SLIP, 2003)