An Intermediate Level HDL for System Level Design. - Jean-Pierre David; Etienne Bergeron (FDL, 2004)

A Step towards Intelligent Translation from High-Level Design to RTL. - Jean-Pierre David; Etienne Bergeron (IWSOC, 2004)

High Level Synthesis for Data-Driven Applications. - Etienne Bergeron; Xavier Saint-Mleux; Marc Feeley; Jean-Pierre David (IEEE International Workshop on Rapid System Prototyping, 2005)

Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs. - Etienne Bergeron; Marc Feeley; Jean-Pierre David (CC, 2008)

Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation. - Etienne Bergeron; Louis-David Perron; Marc Feeley; Jean-Pierre David (ACM Trans. Reconfigurable Technol. Syst., 2011)