Power dissipation in one-latch and two-latch double edge triggered flip-flops. - Antonio G. M. Strollo; Carlo Cimino; Ettore Napoli (ICECS, 1999)

A VLSI processor for light-weight real-time SAR imaging using signum coded signal and time domain processing. - Antonio G. M. Strollo; Ettore Napoli; Carlo Cimino (ICECS, 1999)

New clock-gating techniques for low-power flip-flops. - Antonio G. M. Strollo; Ettore Napoli; Davide De Caro (ISLPED, 2000)

Analysis of power dissipation in double edge-triggered flip-flops. - Antonio G. M. Strollo; Ettore Napoli; Carlo Cimino (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Test pattern generator for hybrid testing of combinational circuits. - Davide De Caro; Nicola Mazzocca; Ettore Napoli; Giacinto Paolo Saggese; Antonio G. M. Strollo (ICECS, 2001)

New design of squarer circuits using Booth encoding and folding techniques. - Antonio G. M. Strollo; Ettore Napoli; Davide De Caro (ICECS, 2001)

A reconfigurable 2D convolver for real-time SAR imaging. - Antonio G. M. Strollo; Ettore Napoli; Davide De Caro; Giacinto Paolo Saggese (ICECS, 2001)

ROM-less direct digital frequency synthesizers exploiting polynomial approximation. - Davide De Caro; Ettore Napoli; Antonio G. M. Strollo (ICECS, 2002)

Direct digital frequency synthesis with dual-slope approach. - Antonio Giuseppe Maria Strollo; Davide De Caro; Ettore Napoli; Nicola Petra (ESSCIRC, 2003)

High-speed direct digital frequency synthesizers in 0.25-μm CMOS. - Antonio G. M. Strollo; Davide De Caro; Ettore Napoli; Nicola Petra (CICC, 2004)

An area-efficient high-speed Reed-Solomon decoder in 0.25 μm CMOS. - Antonio Giuseppe Maria Strollo; Nicola Petra; Davide De Caro; Ettore Napoli (ESSCIRC, 2004)

Direct digital frequency synthesizers with polynomial hyperfolding technique. - Davide De Caro; Ettore Napoli; Antonio G. M. Strollo (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

A high-speed sense-amplifier based flip-flop. - Davide De Caro; Ettore Napoli; Nicola Petra; Antonio G. M. Strollo (ECCTD, 2005)

A novel high-speed sense-amplifier-based flip-flop. - Antonio G. M. Strollo; Davide De Caro; Ettore Napoli; Nicola Petra (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Code compression for ARM7 embedded systems. - Valeria Garofalo; Ettore Napoli; Nicola Petra; Antonio Giuseppe Maria Strollo (ECCTD, 2007)

Limits and application of the newly proposed deep-depletion SOI LDMOS. - Ettore Napoli (IET Circuits Devices Syst., 2007)

Study of a failure mechanism during UIS switching of planar PT-IGBT with current sense cell. - Giovanni Breglio; Andrea Irace; Ettore Napoli; Paolo Spirito; Kimimori Hamada; T. Nishijima; T. Ueta (Microelectron. Reliab., 2007)

Low error truncated multipliers for DSP applications. - Valeria Garofalo; Nicola Petra; Davide De Caro; Antonio G. M. Strollo; Ettore Napoli (ICECS, 2008)

Constrained piecewise polinomial approximation for hardware implementation of elementary functions. - Antonio G. M. Strollo; Davide De Caro; Nicola Petra; Ettore Napoli; Valeria Garofalo (ICECS, 2008)

Detection of localized UIS failure on IGBTs with the aid of lock-in thermography. - Giovanni Breglio; Andrea Irace; Ettore Napoli; Michele Riccio; Paolo Spirito; Kimimori Hamada; T. Nishijima; T. Ueta (Microelectron. Reliab., 2008)

1300 V, 2 ms pulse inductive load switching test circuit with 20 ns selectable crowbar intervention. - Lucio Rossi; Michele Riccio; Ettore Napoli; Andrea Irace; Giovanni Breglio; Paolo Spirito (Microelectron. Reliab., 2009)

High-speed differential resistor ladder for A/D converters. - Davide De Caro; Marino Coppola; Nicola Petra; Ettore Napoli; Antonio G. M. Strollo; Valeria Garofalo (ISCAS, 2010)

A novel truncated squarer with linear compensation function. - Valeria Garofalo; Marino Coppola; Davide De Caro; Ettore Napoli; Nicola Petra; Antonio G. M. Strollo (ISCAS, 2010)

Fixed-width CSD multipliers with minimum mean square error. - Nicola Petra; Davide De Caro; Antonio G. M. Strollo; Valeria Garofalo; Ettore Napoli; Marino Coppola; Pietro Todisco (ISCAS, 2010)

Analysis of large area Trench-IGBT current distribution under UIS test with the aid of lock-in thermography. - Michele Riccio; Lucio Rossi; Andrea Irace; Ettore Napoli; Giovanni Breglio; Paolo Spirito; Ryuzo Tagami; Yoshihito Mizuno (Microelectron. Reliab., 2010)

A novel UIS test system with Crowbar feedback for reduced failure energy in power devices testing. - Lucio Rossi; Michele Riccio; Ettore Napoli; Andrea Irace; Giovanni Breglio; Paolo Spirito (Microelectron. Reliab., 2010)

Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error. - Nicola Petra; Davide De Caro; Valeria Garofalo; Ettore Napoli; Antonio G. M. Strollo (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error. - Valeria Garofalo; Nicola Petra; Ettore Napoli (IEEE Trans. Computers, 2011)

Design of Fixed-Width Multipliers With Linear Compensation Function. - Nicola Petra; Davide De Caro; Valeria Garofalo; Ettore Napoli; Antonio G. M. Strollo (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

FPGA implementation of OpenCV compatible background identification circuit. - Mariangela Genovese; Ettore Napoli (CompIMAGE, 2012)

An FPGA-based Real-time Background Identification Circuit for 1080p Video. - Mariangela Genovese; Ettore Napoli (SITIS, 2012)

3D electro-thermal simulations of wide area power devices operating in avalanche condition. - Michele Riccio; Giuseppe De Falco; Luca Maresca; Giovanni Breglio; Ettore Napoli; Andrea Irace; Yohei Iwahashi; Paolo Spirito (Microelectron. Reliab., 2012)

Implementation of a pulse-holding Time-to-Digital Converter on an FPGA. - Francesco Brandonisio; Alberto Prodomo; Michael Peter Kennedy; Ettore Napoli (ECCTD, 2013)

FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video. - Mariangela Genovese; Ettore Napoli; Davide De Caro; Nicola Petra; Antonio G. M. Strollo (J. Electr. Comput. Eng., 2013)

FPGA-based architecture for real time segmentation and denoising of HD video. - Mariangela Genovese; Ettore Napoli (J. Real Time Image Process., 2013)

NORA based TDC in 90 nm CMOS. - Nicola Petra; Sebastiano Russo; Davide De Caro; Ettore Napoli; Giancarlo Barbarino; Antonio G. M. Strollo (Microelectron. J., 2013)

Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error. - Davide De Caro; Nicola Petra; Antonio Giuseppe Maria Strollo; Fabio Tessitore; Ettore Napoli (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Towards a Frequency Domain Processor for Real-Time SIFT-based Filtering. - Giorgio Lopez; Ettore Napoli; Antonio G. M. Strollo (ApplePies, 2014)

Hardware performance versus video quality trade-off for Gaussian mixture model based background identification systems. - Mariangela Genovese; Ettore Napoli; Nicola Petra (ICDIP, 2014)

FPGA based system for the generation of noise with programmable power spectrum. - Ettore Napoli; Mauro D'Arco; Pasquale Di Cosmo; Mariangela Genovese; Antonio G. M. Strollo (ISCAS, 2014)

A Frequency Domain Processor for Real-Time CDVS Keypoints Extraction. - Giorgio Lopez; Ettore Napoli; Antonio G. M. Strollo (SITIS, 2014)

Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA. - Mariangela Genovese; Ettore Napoli; Davide De Caro; Nicola Petra; Antonio G. M. Strollo (Integr., 2014)

Truncated squarer with minimum mean-square error. - Nicola Petra; Davide De Caro; Valeria Garofalo; Ettore Napoli; Antonio G. M. Strollo (Microelectron. J., 2014)

Accurate Fixed-Point Logarithmic Converter. - Davide De Caro; Mariangela Genovese; Ettore Napoli; Nicola Petra; Antonio G. M. Strollo (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

High Speed Speculative Multipliers Based on Speculative Carry-Save Tree. - Alessandro Cilardo; Davide De Caro; Nicola Petra; Francesco Caserta; Nicola Mazzocca; Ettore Napoli; Antonio Giuseppe Maria Strollo (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Design and Implementation of a Preprocessing Circuit for Bandpass Signals Acquisition. - Mauro D'Arco; Mariangela Genovese; Ettore Napoli; Michele Vadursi (IEEE Trans. Instrum. Meas., 2014)

ASIC and FPGA Implementation of the Gaussian Mixture Model Algorithm for Real-Time Segmentation of High Definition Video. - Mariangela Genovese; Ettore Napoli (IEEE Trans. Very Large Scale Integr. Syst., 2014)

The noise and spur delusion in fractional-N frequency synthesizer design. - Michael Peter Kennedy; Hongjia Mo; Zhida Li; Guosheng Hu; Paolo Scognamiglio; Ettore Napoli (ISCAS, 2015)

An FPGA processor for real-time, fixed-point refinement of CDVS keypoints. - Giorgio Lopez; Ettore Napoli; Domenico Meglio; Antonio G. M. Strollo (ISCAS, 2015)

FPGA implementation of the CCSDS-123.0-B-1 lossless Hyperspectral Image compression algorithm prediction stage. - Giorgio Lopez; Ettore Napoli; Antonio G. M. Strollo (LASCAS, 2015)

Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images. - Mariangela Genovese; Paolo Bifulco; Davide De Caro; Ettore Napoli; Nicola Petra; Maria Romano; Mario Cesarelli; Antonio G. M. Strollo (Integr., 2015)

A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS. - Davide De Caro; Fabio Tessitore; Gianfranco Vai; Nicola Imperato; Nicola Petra; Ettore Napoli; Claudio Parrella; Antonio G. M. Strollo (IEEE J. Solid State Circuits, 2015)

Variable Latency Speculative Han-Carlson Adder. - Darjn Esposito; Davide De Caro; Ettore Napoli; Nicola Petra; Antonio Giuseppe Maria Strollo (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs. - Darjn Esposito; Gerardo Castellano; Davide De Caro; Ettore Napoli; Nicola Petra; Antonio G. M. Strollo (ISCAS, 2016)

Comparative analysis of differential colpitts and cross-coupled VCOs in 180 nm Si-Ge HBT technology. - Valerio Marotta; Giuseppe Macera; Michael Peter Kennedy; Ettore Napoli (ISCAS, 2016)

Digital circuit for the generation of colored noise exploiting single bit pseudo random sequence. - Ettore Napoli; Gerardo Castellano; Darjn Esposito; Antonio G. M. Strollo (LASCAS, 2016)

On the use of approximate adders in carry-save multiplier-accumulators. - Darjn Esposito; Davide De Caro; Ettore Napoli; Nicola Petra; Antonio G. M. Strollo (ISCAS, 2017)

Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines. - Davide De Caro; Fabio Tessitore; Gianfranco Vai; Gerardo Castellano; Ettore Napoli; Nicola Petra; Claudio Parrella; Antonio G. M. Strollo (Circuits Syst. Signal Process., 2017)

A SISO Register Circuit Tailored for Input Data with Low Transition Probability. - Ettore Napoli; Gerardo Castellano; Davide De Caro; Darjn Esposito; Nicola Petra; Antonio G. M. Strollo (IEEE Trans. Computers, 2017)

Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding. - Davide De Caro; Ettore Napoli; Darjn Esposito; Gerardo Castellano; Nicola Petra; Antonio G. M. Strollo (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise. - Ettore Napoli; Gerardo Castellano; Davide De Caro; Darjn Esposito; Nicola Petra; Antonio Giuseppe Maria Strollo (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Design of Low-Power Approximate LMS Filters with Precision-Scalability. - Darjn Esposito; Gennaro Di Meo; Davide De Caro; Antonio G. M. Strollo; Ettore Napoli (ApplePies, 2018)

Quality-Scalable Approximate LMS Filter. - Darjn Esposito; Gennaro Di Meo; Davide De Caro; Antonio G. M. Strollo; Ettore Napoli (ICECS, 2018)

On the Use of Approximate Multipliers in LMS Adaptive Filters. - Darjn Esposito; Gennaro Di Meo; Davide De Caro; Nicola Petra; Ettore Napoli; Antonio G. M. Strollo (ISCAS, 2018)

Stall-Aware Fixed-Point Implementation of LMS Filters. - Darjn Esposito; Gennaro Di Meo; Davide De Caro; Ettore Napoli; Nicola Petra; Antonio G. M. Strollo (PRIME, 2018)

Approximate Multipliers Based on New Approximate Compressors. - Darjn Esposito; Antonio Giuseppe Maria Strollo; Ettore Napoli; Davide De Caro; Nicola Petra (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Standard-Cell-Based All-Digital PWM Modulator With High Resolution and Spread- Spectrum Capability. - Michele De Martino; Davide De Caro; Darjn Esposito; Ettore Napoli; Nicola Petra; Antonio Giuseppe Maria Strollo (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Digital Circuit for the Arbitrary Selection of Sample Rate in Digital Storage Oscilloscopes. - Mauro D'Arco; Ettore Napoli; Efstratios Zacharelos (ApplePies, 2019)

Variable-Rounded LMS Filter for Low-Power Applications. - Gennaro Di Meo; Davide De Caro; Ettore Napoli; Nicola Petra; Antonio G. M. Strollo (ApplePies, 2019)

An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy. - Gerardo Castellano; Davide De Caro; Darjn Esposito; Paolo Bifulco; Ettore Napoli; Nicola Petra; Emilio Andreozzi; Mario Cesarelli; Antonio G. M. Strollo (Circuits Syst. Signal Process., 2019)

Low-Power Hardware Implementation of Least-Mean-Square Adaptive Filters Using Approximate Arithmetic. - Darjn Esposito; Davide De Caro; Gennaro Di Meo; Ettore Napoli; Antonio G. M. Strollo (Circuits Syst. Signal Process., 2019)

Low-power Implementation of LMS Adaptive Filters Using Scalable Rounding. - Gennaro Di Meo; Davide De Caro; Ettore Napoli; Nicola Petra; Antonio G. M. Strollo (ICECS, 2020)

Low-Power Approximate Multiplier with Error Recovery using a New Approximate 4-2 Compressor. - Antonio G. M. Strollo; Davide De Caro; Ettore Napoli; Nicola Petra; Gennaro Di Meo (ISCAS, 2020)

Digital Circuit for Seamless Resampling ADC Output Streams. - Mauro D'Arco; Ettore Napoli; Efstratios Zacharelos (Sensors, 2020)

A 1.45 GHz All-Digital Spread Spectrum Clock Generator in 65nm CMOS for Synchronization-Free SoC Applications. - Davide De Caro; Gennaro Di Meo; Ettore Napoli; Nicola Petra; Antonio Giuseppe Maria Strollo (IEEE Trans. Circuits Syst., 2020)

A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate. - Ettore Napoli; Davide De Caro; Nicola Petra; Antonio Giuseppe Maria Strollo (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers. - Antonio Giuseppe Maria Strollo; Ettore Napoli; Davide De Caro; Nicola Petra; Gennaro Di Meo (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A Time Base Option for Arbitrary Selection of Sample Rate in Digital Storage Oscilloscopes. - Mauro D'Arco; Ettore Napoli; Leopoldo Angrisani (IEEE Trans. Instrum. Meas., 2020)

Real-Time Downsampling in Digital Storage Oscilloscopes With Multichannel Architectures. - Ettore Napoli; Efstratios Zacharelos; Mauro D'Arco; Antonio Giuseppe Maria Strollo (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Approximate Recursive Multipliers Using Carry Truncation and Error Compensation. - Italo Nunziata; Efstratios Zacharelos; Gerardo Saggese; Antonio Giuseppe Maria Strollo; Ettore Napoli (PRIME, 2022)

Enabling Fine Sample Rate Settings in DSOs with Time-Interleaved ADCs. - Mauro D'Arco; Ettore Napoli; Efstratios Zacharelos; Leopoldo Angrisani; Antonio Giuseppe Maria Strollo (Sensors, 2022)

A Novel Module-Sign Low-Power Implementation for the DLMS Adaptive Filter With Low Steady-State Error. - Gennaro Di Meo; Davide De Caro; Giacinto Paolo Saggese; Ettore Napoli; Nicola Petra; Antonio Giuseppe Maria Strollo (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements. - Antonio Giuseppe Maria Strollo; Ettore Napoli; Davide De Caro; Nicola Petra; Giacinto Paolo Saggese; Gennaro Di Meo (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Approximate Recursive Multipliers Using Low Power Building Blocks. - Efstratios Zacharelos; Italo Nunziata; Gerardo Saggese; Antonio G. M. Strollo; Ettore Napoli (IEEE Trans. Emerg. Top. Comput., 2022)

On-Chip Spike Detection and Classification using Neural Networks and Approximate Computing. - Efstratios Zacharelos; Ciro Scognamillo; Ettore Napoli; Diego Gragnaniello (BioCAS, 2023)

CFPM: Run-time Configurable Floating-Point Multiplier. - Gerardo Saggese; Ettore Napoli; Antonio Giuseppe Maria Strollo (PRIME, 2023)

Approximate squaring circuits exploiting recursive architectures. - Efstratios Zacharelos; Italo Nunziata; Gerardo Saggese; Antonio G. M. Strollo; Ettore Napoli (Integr., 2023)

Comprehensive Analysis of Input Order Invariant Approximate 4-2 Compressors for Binary Multipliers. - Ettore Napoli; Antonio G. M. Strollo; Efstratios Zacharelos; Gennaro Di Meo (ISCAS, 2024)

Approximate Full-Adders: A Comprehensive Analysis. - Ettore Napoli; Efstratios Zacharelos; Antonio G. M. Strollo; Gennaro Di Meo (IEEE Access, 2024)

A novel approximate multiplier based on improved logarithmic and antilogarithmic conversions. - Gennaro Di Meo; Davide De Caro; Luca Tegazzini; Ettore Napoli; Antonio G. M. Strollo (ISCAS, 2025)

Towards the Design of a Real-Time Processing System for Forcecardiography Signals. - Efstratios Zacharelos; Emilio Andreozzi; Daniele Esposito; Martino Giaquinto; Ettore Napoli (MOCAST, 2025)

Low-Power High Precision Floating-Point Divider With Bidimensional Linear Approximation. - Gennaro Di Meo; Antonio Giuseppe Maria Strollo; Davide De Caro; Luca Tegazzini; Ettore Napoli (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)