Operation tables for scheduling in the presence of incomplete bypassing. - Aviral Shrivastava; Eugene Earlie; Nikil D. Dutt; Alexandru Nicolau (CODES+ISSS, 2004)

Aggregating processor free time for energy reduction. - Aviral Shrivastava; Eugene Earlie; Nikil D. Dutt; Alexandru Nicolau (CODES+ISSS, 2005)

PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors. - Aviral Shrivastava; Nikil D. Dutt; Alexandru Nicolau; Eugene Earlie (DATE, 2005)

Automatic generation of operation tables for fast exploration of bypasses in embedded processors. - Sanghyun Park; Eugene Earlie; Aviral Shrivastava; Alex Nicolau; Nikil D. Dutt; Yunheung Paek (DATE, 2006)

Bypass aware instruction scheduling for register file power reduction. - Sanghyun Park; Aviral Shrivastava; Nikil D. Dutt; Alexandru Nicolau; Yunheung Paek; Eugene Earlie (LCTES, 2006)

Retargetable pipeline hazard detection for partially bypassed processors. - Aviral Shrivastava; Eugene Earlie; Nikil D. Dutt; Alexandru Nicolau (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Automatic Design Space Exploration of Register Bypasses in Embedded Processors. - Aviral Shrivastava; Sanghyun Park; Eugene Earlie; Nikil D. Dutt; Alexandru Nicolau; Yunheung Paek (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Register File Power Reduction Using Bypass Sensitive Compiler. - Sanghyun Park; Aviral Shrivastava; Nikil D. Dutt; Alexandru Nicolau; Yunheung Paek; Eugene Earlie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)