Delay testable sequential circuit designs. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov; Virendra Singh (EWDTS, 2013)

Combinational part structure simplification of fully delay testable sequential circuit. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov; Elena Roumjantseva (EWDTS, 2014)

Multiple stuck-at fault testability of a combinational circuit derived by covering ROBDD nodes by Invert-And-Or sub-circuits. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov; Toral Shah (EWDTS, 2015)

Simplification of fully delay testable combinational circuits. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov; Toral Shah (IOLTS, 2015)

Pseudo-exhaustive testing of sequential circuits for multiple stuck-at faults. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov (EWDTS, 2016)

Preventing and masking Trojan circuits triggering out of working area. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov; Sergei Ostanin; Irina Kirienko (ECCTD, 2017)

Detection and masking of Trojan Circuits in sequential logic. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov; Sergey Ostanin; Ekaterina Nikolaeva (EWDTS, 2017)

Trojan circuits preventing and masking in sequential circuits. - Anjela Yu. Matrosova; Eugeniy Mitrofanov; Sergei Ostanin; Irina Kirienko (IOLTS, 2017)