Dynamic Power Management for non-stationary service requests. - Eui-Young Chung; Luca Benini; Alessandro Bogliolo; Giovanni De Micheli (DATE, 1999)

Dynamic power management using adaptive learning tree. - Eui-Young Chung; Luca Benini; Giovanni De Micheli (ICCAD, 1999)

Quantitative Comparison of Power Management Algorithms. - Yung-Hsiang Lu; Eui-Young Chung; Tajana Simunic; Giovanni De Micheli; Luca Benini (DATE, 2000)

Automatic source code specialization for energy reduction. - Eui-Young Chung; Luca Benini; Giovanni De Micheli (ISLPED, 2001)

Source code transformation based on software cost analysis. - Eui-Young Chung; Luca Benini; Giovanni De Micheli (ISSS, 2001)

Contents provider-assisted dynamic voltage scaling for low energy multimedia applications. - Eui-Young Chung; Giovanni De Micheli; Luca Benini (ISLPED, 2002)

Dynamic Power Management for Nonstationary Service Requests. - Eui-Young Chung; Luca Benini; Alessandro Bogliolo; Yung-Hsiang Lu; Giovanni De Micheli (IEEE Trans. Computers, 2002)

Value-sensitive automatic code specialization for embedded software. - Eui-Young Chung; Luca Benini; Giovanni De Micheli; Gabriele Luculli; Marco Carilli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design. - Chulho Shin; Young-Taek Kim; Eui-Young Chung; Kyu-Myung Choi; Jeong-Taek Kong; Soo-Kwan Eo (DATE, 2004)

Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture. - Young-Taek Kim; Taehun Kim; Youngduk Kim; Chulho Shin; Eui-Young Chung; Kyu-Myung Choi; Jeong-Taek Kong; Soo-Kwan Eo (DATE, 2005)

PowerViP: Soc power estimation framework at transaction level. - Ikhwan Lee; Hyunsuk Kim; Peng Yang; Sungjoo Yoo; Eui-Young Chung; Kyu-Myung Choi; Jeong-Taek Kong; Soo-Kwan Eo (ASP-DAC, 2006)

Worst case execution time analysis for synthesized hardware. - Jun-hee Yoo; Xingguang Feng; Kiyoung Choi; Eui-Young Chung; Kyu-Myung Choi (ASP-DAC, 2006)

Demand paging for OneNANDTM Flash eXecute-in-place. - Yongsoo Joo; Yongseok Choi; Chanik Park; Sung Woo Chung; Eui-Young Chung; Naehyuck Chang (CODES+ISSS, 2006)

Exploiting Binary Abstractions in Deciphering Gene Interactions. - Sungroh Yoon; Abhishek Garg; Eui-Young Chung; Hyun Seok Park; Woong-Yang Park; Giovanni De Micheli (EMBC, 2006)

Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems. - Minje Jun; Kwanhu Bang; Hyuk-Jun Lee; Naehyuck Chang; Eui-Young Chung (ASP-DAC, 2007)

Is the Complicated ECC Array Necessary for Data Caches? - Eui-Young Chung; Hyo-Joong Suh; Cheol Hong Kim; Sung Woo Chung (CDES, 2007)

Clustering protein environments for function prediction: finding PROSITE motifs in 3D. - Sungroh Yoon; Jessica C. Ebert; Eui-Young Chung; Giovanni De Micheli; Russ B. Altman (BMC Bioinform., 2007)

Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis. - Eui-Young Chung; Hyuk-Jun Lee; Sung Woo Chung (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Latency-Aware Bus Arbitration for Real-Time Embedded Systems. - Minje Jun; Kwanhu Bang; Hyuk-Jun Lee; Eui-Young Chung (IEICE Trans. Inf. Syst., 2007)

Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches. - Minje Jun; Sungjoo Yoo; Eui-Young Chung (ASP-DAC, 2008)

An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching. - Eui-Young Chung; Cheol Hong Kim; Sung Woo Chung (DELTA, 2008)

Extended MPEG Video Format for Efficient Dynamic Voltage Scaling. - Kwanhu Bang; Sung-Yong Bang; Eui-Young Chung (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective. - Soong Hyun Shin; Sung Woo Chung; Eui-Young Chung; Chu Shik Jhon (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Energy and Performance Optimization of Demand Paging With OneNAND Flash. - Yongsoo Joo; Yongseok Choi; Jaehyun Park 005; Chanik Park; Sung Woo Chung; Eui-Young Chung; Naehyuck Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory. - Hyuk-Jun Lee; Eui-Young Chung (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Energy-optimal dynamic thermal management for green computing. - Donghwa Shin; Jihun Kim; Naehyuck Chang; Jinhang Choi; Sung Woo Chung; Eui-Young Chung (ICCAD, 2009)

A robust peak detection method for RNA structure inference by high-throughput contact mapping. - Jinkyu Kim 001; Seunghak Yu; Byonghyo Shim; Hanjoo Kim; Hyeyoung Min; Eui-Young Chung; Rhiju Das; Sungroh Yoon (Bioinform., 2009)

K-maximin clustering: a maximin correlation approach to partition-based clustering. - Taehoon Lee 001; Seung Jean Kim; Eui-Young Chung; Sungroh Yoon (IEICE Electron. Express, 2009)

Solid-State Disk with Double Data Rate DRAM Interface for High-Performance PCs. - Dong Kim; Kwanhu Bang; Seung-Hwan Ha; Chanik Park; Sung Woo Chung; Eui-Young Chung (IEICE Trans. Inf. Syst., 2009)

Jitter-Conscious Bus Arbitration Scheme for Real-Time Systems. - Jong-Ho Roh; Minje Jun; Kwanhu Bang; Eui-Young Chung (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling. - Sung-Yong Bang; Kwanhu Bang; Sungroh Yoon; Eui-Young Chung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Topology Synthesis of Cascaded Crossbar Switches. - Minje Jun; Sungjoo Yoo; Eui-Young Chung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

High-Speed Post-Layout Logic Simulation Using Quasi-Static Clock Event Evaluation. - Myeongjin Kim; Eui-Young Chung; Sungroh Yoon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Design and analysis of flash translation layers for multi-channel NAND flash-based storage devices. - Sang-Hoon Park; Seung-Hwan Ha; Kwanhu Bang; Eui-Young Chung (IEEE Trans. Consumer Electron., 2009)

Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network. - Minje Jun; Sungroh Yoon; Eui-Young Chung (DATE, 2010)

Design of On-Chip Crossbar Network Topology Using Chained Edge Partitioning. - Minje Jun; Eui-Young Chung (Comput. J., 2010)

A fast and simple system performance emulator for enhanced solid state disks: a case study of long read operations. - Do Yeun Kim; Chanik Park; Eui-Young Chung; Sung Woo Chung (J. Zhejiang Univ. Sci. C, 2010)

Architecture Exploration of High-Performance PCs with a Solid-State Disk. - Dong Kim; Kwanhu Bang; Seung-Hwan Ha; Sungroh Yoon; Eui-Young Chung (IEEE Trans. Computers, 2010)

On the Thermal Attack in Instruction Caches. - Joonho Kong; Johnsy K. John; Eui-Young Chung; Sung Woo Chung; Jie S. Hu (IEEE Trans. Dependable Secur. Comput., 2010)

Energy-Optimal Dynamic Thermal Management: Computation and Cooling Power Co-Optimization. - Donghwa Shin; Sung Woo Chung; Eui-Young Chung; Naehyuck Chang (IEEE Trans. Ind. Informatics, 2010)

High-voltage wordline generator for low-power program operation in NAND flash memories. - Samkyu Won; Yujong Noh; Hyunchul Cho; Jeil Ryu; Sungwook Choi; Sungdae Choi; DuckJu Kim; Junseop Chung; Bong-Seok Han; Eui-Young Chung (A-SSCC, 2011)

Asymmetric DRAM synthesis for heterogeneous chip multiprocessors in 3D-stacked architecture. - Minje Jun; Myoung-Jin Kim; Eui-Young Chung (ICCAD, 2012)

Analytical memory bandwidth model for many-core processor based systems. - Hyuk-Jun Lee; Woo-Cheol Cho; Eui-Young Chung (IEICE Electron. Express, 2012)

Partial Connection-Aware Topology Synthesis for On-Chip Cascaded Crossbar Network. - Minje Jun; Deumji Woo; Eui-Young Chung (IEEE Trans. Computers, 2012)

Application-Support Particle Filter for Dynamic Voltage Scaling of Multimedia Applications. - Jae-Beom Lee; Myoung-Jin Kim; Sungroh Yoon; Eui-Young Chung (IEEE Trans. Computers, 2012)

GPU-based acceleration of an RNA tertiary structure prediction algorithm. - Yongkweon Jeon; Eesuk Jung; Hyeyoung Min; Eui-Young Chung; Sungroh Yoon (Comput. Biol. Medicine, 2013)

Page overwriting method for performance improvement of NAND flash memories. - Samkyu Won; Eui-Young Chung; DuckJu Kim; Junseop Chung; Bong-Seok Han; Hyuk-Jun Lee (IEICE Electron. Express, 2013)

Power Failure Protection Scheme for Reliable High-Performance Solid State Disks. - Kwanhu Bang; Kyung-Il Im; Dong-gun Kim; Sang-Hoon Park; Eui-Young Chung (IEICE Trans. Inf. Syst., 2013)

A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method. - Hyuk-Jun Lee; Seung-Chul Kim; Eui-Young Chung (IEICE Trans. Inf. Syst., 2013)

An Energy and Performance Efficient DVFS Scheme for Irregular Parallel Divide-and-Conquer Algorithms on the Intel SCC. - Yu-Liang Chou; Shaoshan Liu; Eui-Young Chung; Jean-Luc Gaudiot (IEEE Comput. Archit. Lett., 2014)

Design of a bitmap-based QoS-aware memory controller for a packet memory. - Seunghak Yu; Sungroh Yoon; Eui-Young Chung; Hyuk-Jun Lee (IEICE Electron. Express, 2014)

Exploiting Implementation Diversity and Partial Connection of Routers in Application-Specific Network-on-Chip Topology Synthesis. - Minje Jun; Won Woo Ro; Eui-Young Chung (IEEE Trans. Computers, 2014)

$C ! !- ! !Lock$ : Energy Efficient Synchronization for Embedded Multicore Systems. - Seung-Hun Kim; Sang Hyong Lee; Minje Jun; Byunghoon Lee; Won Woo Ro; Eui-Young Chung; Jean-Luc Gaudiot (IEEE Trans. Computers, 2014)

An Adaptive Idle-Time Exploiting Method for Low Latency NAND Flash-Based Storage Devices. - Sang-Hoon Park; Dong-gun Kim; Kwanhu Bang; Hyuk-Jun Lee; Sungjoo Yoo; Eui-Young Chung (IEEE Trans. Computers, 2014)

A High-Performance Solid-State Disk with Double-Data-Rate NAND Flash Memory. - Eui-Young Chung; Chang-Il Son; Kwanhu Bang; Dong Kim; Soong-Mann Shin; Sungroh Yoon (CoRR, 2015)

FRAME: Fast and Realistic Attacker Modeling and Evaluation for Temporal Logical Correlation in Static Noise. - Sungroh Yoon; Nahmsuk Oh; Peivand F. Tehrani; Eui-Young Chung; Giovanni De Micheli (CoRR, 2015)

PIM architecture exploration for HMC. - Sangwoo Han; Hyeokjun Seo; Byoung Jin Kim; Eui-Young Chung (APCCAS, 2016)

A RAM cache approach using host memory buffer of the NVMe interface. - JuHyung Hong; Sangwoo Han; Eui-Young Chung (ISOCC, 2016)

FPGA power estimation simulator for dynamic input data. - Tae-Hee You; Jeongbin Kim 001; Minyoung Im; Eui-Young Chung (ISOCC, 2016)

Near-Data Processing for Machine Learning. - Hyeokjun Choe; Seil Lee; Seongsik Park; Sei Joon Kim; Eui-Young Chung; Sungroh Yoon (CoRR, 2016)

NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices. - Jinyoung Kim; Sang-Hoon Park; Hyeokjun Seo; Ki-Whan Song; Sungroh Yoon; Eui-Young Chung (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Timing window wiper: A new scheme for reducing refresh power of DRAM. - Ho Hyun Shin; Hyeokjun Seo; Byunghoon Lee; Jeongbin Kim 001; Eui-Young Chung (ASP-DAC, 2017)

An effective pre-store/pre-load method exploiting intra-request idle time of NAND flash-based storage devices. - Jin-Young Kim; Tae-Hee You; Hyeokjun Seo; Sungroh Yoon; Jean-Luc Gaudiot; Eui-Young Chung (Microprocess. Microsystems, 2017)

Scalable Bandwidth Shaping Scheme via Adaptively Managed Parallel Heaps in Manycore-Based Network Processors. - Taehyun Kim; Jongbum Lim; Jinku Kim; Woo-Cheol Cho; Eui-Young Chung; Hyuk-Jun Lee (ACM Trans. Design Autom. Electr. Syst., 2017)

A Study of Data Layout in Multi-channel Processing-In-Memory Architecture. - Taeyang Jeong; Duheon Choi; Sangwoo Han; Eui-Young Chung (ICSCA, 2018)

CAD Tool Flow for Variation-Tolerant Non-Volatile STT-MRAM LUT based FPGA. - Jeongbin Kim 001; Ki Tae Kim; Eui-Young Chung (ICSCA, 2018)

Asymmetric Slew Logic Threshold Method on Near Threshold Region. - Young Min Park; Kwangsu Kim; Byoung Jin Kim; Eui-Young Chung (ICSCA, 2018)

EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory. - Ho Hyun Shin; Young Min Park; Duheon Choi; Byoung Jin Kim; Dae-Hyung Cho; Eui-Young Chung (IEEE Trans. Computers, 2018)

Replacement Policy Adaptable Miss Curve Estimation for Efficient Cache Partitioning. - Byunghoon Lee; Kwangsu Kim; Eui-Young Chung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

ICS: Interrupt-Based Channel Sneaking for Maximally Exploiting Die-Level Parallelism of NAND Flash-Based Storage Devices. - JuHyung Hong; Sangwoo Han; Young Min Park; Eui-Young Chung (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Locality-Aware Compression Scheme for Highly Reliable Embedded Systems. - JuHyung Hong; Jeongbin Kim 001; Sangwoo Han; Eui-Young Chung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A Novel NAND Flash Memory Architecture for Maximally Exploiting Plane-Level Parallelism. - Myeongjin Kim; Wontaeck Jung; Hyukjun Lee; Eui-Young Chung (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Asymmetric Prefetching Architecture for Multicore Processor. - Duheon Choi; Kwangsu Kim; Eui-Young Chung (ISOCC, 2020)

A Fast Full-System Simulation Environment for Memory System Evaluation. - Taeyang Jeong; Sangwoo Han; Eui-Young Chung (ISOCC, 2020)

Resource Utilization Optimized Design Method for Matched Filter of PSS Searcher. - Dohyun Kim; Taeyang Jeong; Eui-Young Chung (ISOCC, 2020)

Exploring Replacement Policy for Memcached. - Gi Lee; Byoung Jin Kim; Eui-Young Chung (ISOCC, 2020)

The necessity of anterior knowledge exchange activities for technological collaboration and innovation performance improvement. - Eui-Young Chung; Kibaek Lee (Int. J. Technol. Manag., 2020)

Per-Operation Reusability Based Allocation and Migration Policy for Hybrid Cache. - Minsik Oh; Kwangsu Kim; Duheon Choi; Hyukjun Lee; Eui-Young Chung (IEEE Trans. Computers, 2020)

Multitoken-Based Power Management for NAND Flash Storage Devices. - Tae-Hee You; Sangwoo Han; Young Min Park; Hyuk-Jun Lee; Eui-Young Chung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Cross-Corner Delay Variation Model for Standard Cell Libraries. - Kwangsu Kim; Byungha Joo; Young Min Park; Taeyang Jeong; Ki Tae Kim; Eui-Young Chung (IEEE Access, 2021)

Energy-Efficient Shared Cache Using Way Prediction Based on Way Access Dominance Detection. - Yun-Seok Oh; Eui-Young Chung (IEEE Access, 2021)

Quant-PIM: An Energy-Efficient Processing-in-Memory Accelerator for Layerwise Quantized Neural Networks. - Young Seo Lee; Eui-Young Chung; Young-Ho Gong; Sung Woo Chung (IEEE Embed. Syst. Lett., 2021)

STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment. - Jeongbin Kim 001; Yongwoon Song; Kyungseon Cho; Hyukjun Lee; Hongil Yoon; Eui-Young Chung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Adaptive Tag Comparison for Hybrid Cache. - Seong Jae Eom; Eui-Young Chung (ISOCC, 2023)

Developing a Job Search Platform for SMEs to Resolve Job Mismatch: A Case Study. - Junghwan Lee; Eui-Young Chung; Dongwook Kim (Int. J. Asian Bus. Inf. Manag., 2023)

Page Type-Aware Data Migration Technique for Read Disturb Management of NAND Flash Memory. - Sangwoo Han; Minjung Cho; Gi Lee; Eui-Young Chung (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Operand-Oriented Virtual Memory Support for Near-Memory Processing. - Duheon Choi; Taeyang Jeong; Joonhyeok Yeom; Eui-Young Chung (IEEE Trans. Computers, 2023)

Unified Wear-Leveling Technique for NVM-Based Buffer of SSD. - Young Min Park; Joonhyeok Yeom; Dohyun Kim; Eui-Young Chung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Auto Batching Scheme for Optimizing LSTM Inference on FPGA Platforms. - Byoung Jin Kim; Eui-Young Chung (IEEE Access, 2024)

PipePIM: Maximizing Computing Unit Utilization in ML-Oriented Digital PIM by Pipelining and Dual Buffering. - Taeyang Jeong; Eui-Young Chung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

MLCRP: ML-Based GPU Cache Performance Modeling Featured With Reuse Profiles. - Minjung Cho; Eui-Young Chung (IEEE Access, 2025)

AsymGroup: Asymmetric Grouping and Communication Optimization for 2D Tensor Parallelism in LLM Inference. - Ki Tae Kim; Seok-Ju Im; Eui-Young Chung (IEEE Access, 2025)