Statistical Delay Fault Coverage and Defect Level for Delay Faults. - Eun Sei Park; Thomas W. Williams; M. Ray Mercer (ITC, 1988)

A statistical model for delay-fault testing. - Eun Sei Park; M. Ray Mercer; Thomas W. Williams (IEEE Des. Test, 1989)

Delay Testing Quality in Timing-Optimized Designs. - Eun Sei Park; Bill Underwood; Thomas W. Williams; M. Ray Mercer (ITC, 1991)

The Total Delay Fault Model and Statistical Delay Fault Coverage. - Eun Sei Park; M. Ray Mercer; Thomas W. Williams (IEEE Trans. Computers, 1992)

An efficient delay test generation system for combinational logic circuits. - Eun Sei Park; M. Ray Mercer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Switch-Level ATPG Using Constraint-Guided Line Justification. - Eun Sei Park; M. Ray Mercer (ITC, 1993)

Automatic Synthesis of Gate-Level Speed-Independent Control Circuits from Signal Transition Graphs. - Sung Tae Jung; Eun Sei Park; Jung Sik Kim; Chu Shik Jhon (ISCAS, 1995)

An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits. - Byunggyu Kwak; Eun Sei Park (DAC, 1998)