Verification of coarse-grained reconfigurable arrays through random test programs. - Bernhard Egger 002; Eunjin Song; Hochan Lee; Daeyoung Shin (LCTES, 2018)

Random test program generation for verification and validation of the Samsung Reconfigurable Processor. - Bernhard Egger 002; Eunjin Song; Hochan Lee; Daeyong Shin (J. Syst. Archit., 2019)

A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems. - Jang-Woo Lee; Dae-Hoon Na; Anil Kavala; Hwasuk Cho; Junha Lee; Manjae Yang; Eunjin Song; Tongsung Kim; Seon-Kyoo Lee; Dong-Su Jang; Byung-Kwan Chun; Youngmin Jo; et al. (VLSI Circuits, 2020)

A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage. - Dae-Hoon Na; Jang-Woo Lee; Seon-Kyoo Lee; Hwasuk Cho; Junha Lee; Manjae Yang; Eunjin Song; Anil Kavala; Tongsung Kim; Dong-Su Jang; Youngmin Jo; Ji-Yeon Shin; et al. (IEEE J. Solid State Circuits, 2021)

Hyperspace: The Indexing Subsystem of Azure Synapse. - Rahul Potharaju; Terry Kim; Eunjin Song; Wentao Wu 001; Lev Novik; Apoorve Dave; Pouria Pirzadeh; Andrew Fogarty; Gurleen Dhody; Jiying Li; Vidip Acharya; Sinduja Ramanujam; et al. (Proc. VLDB Endow., 2021)