A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process. - Joohwan Kim; Junyoung Park; Jindo Byun; Changkyu Seol; Chang Soo Yoon; EunSeok Shin; Hyunyoon Cho; Youngdo Um; Sucheol Lee; Hyungmin Jin; Kwangseob Shin; Hyunsub Norbert Rie; et al. (CICC, 2022)

A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application. - Hyunsub Norbert Rie; Chang Soo Yoon; Jindo Byun; Sucheol Lee; Garam Kim; Joohwan Kim; Junyoung Park; Hyunyoon Cho; Youngdo Um; Hyungmin Jin; Kwangseob Shin; Minsu Jung; et al. (VLSI Technology and Circuits, 2022)

A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend. - Hyeongmin Seo; Jiyun Han; Kyungmin Kim 003; Baek-Jin Lim; EunSeok Shin; Youngdon Choi; Hyungjong Ko; Jung-Hwan Choi; Sang-Hyun Lee; Changsik Yoo; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2023)