A novel variation insensitive clock distribution methodology. - Ezz El-Din O. Hussein; Yehea I. Ismail (ISCAS, 2010)

A 12Gbps all digital low power SerDes transceiver for on-chip networking. - Sally Safwat; Ezz El-Din O. Hussein; Maged Ghoneima; Yehea I. Ismail (ISCAS, 2011)

A 16Gbps low power self-timed SerDes transceiver for multi-core communication. - Ezz El-Din O. Hussein; Sally Safwat; Maged Ghoneima; Yehea I. Ismail (ISCAS, 2012)

Cairo University SPARC V2 (CUSPARC V2) processor. - S. E.-D. Habib; Mohamed Wagih I. Ismail; Ahmed Ibrahim S. Khalil; Ezz El-Din O. Hussein; Alhassan F. Khedr; Safaa A. Abdelfattah; Ahmed Reda; Mohamed Elgendy (ICM, 2016)