Locatability of Faults in Combinational Networks. - F. Gail Gray; John F. Meyer (IEEE Trans. Computers, 1971)

Reconfiguration for Repair in a Class of Universal Logic Modules. - F. Gail Gray; Richard A. Thompson (IEEE Trans. Computers, 1974)

Multiple Fault Detection in Arrays of Combinational Cells. - B. A. Prasad; F. Gail Gray (IEEE Trans. Computers, 1975)

Algebraic Properties of Functions Affecting Optimum Fault-Tolerant Realizations. - F. Gail Gray; John F. Meyer (IEEE Trans. Computers, 1976)

Fault Detection in Bilateral Arrays of Combinational Cells. - F. Gail Gray; Richard A. Thompson (IEEE Trans. Computers, 1978)

Universal Modular Trees: A Design Procedure. - Richard A. Thompson; F. Gail Gray (IEEE Trans. Computers, 1978)

Diagnosis of Faults in Modular Trees. - F. Gail Gray; Lionel C. C. Shih; Richard A. Thompson (IEEE Trans. Computers, 1979)

Fault Diagnosos in a Boolean n Cube Array of Microprocessors. - James R. Armstrong; F. Gail Gray (IEEE Trans. Computers, 1981)

Tree Structured Sequential Multiple-Valued Logic Design from Universal Modules. - Adit D. Singh; F. Gail Gray; James R. Armstrong (IEEE Trans. Computers, 1981)

Self-Diagnosing Cellular Implementations of Finite-State Machines. - Stephen M. Walters; F. Gail Gray; Richard A. Thompson (IEEE Trans. Computers, 1981)

Significance of problem solving parameters on the performance of combinatorial algorithms on multi-computer parallel architectures. - F. Gail Gray; William M. McCormack; Robert M. Haralick (ICPP, 1982)

A simulation model of a multi-computer system solving a combinatorial problem. - William M. McCormack; F. Gail Gray; Robert M. Haralick (WSC, 1982)

Efficient Graph Automorphism by Vertex Partitioning. - Glenn S. Fowler; Robert M. Haralick; F. Gail Gray; Charles Feustel; Charles M. Grinstead (Artif. Intell., 1983)

A Fault-Tolerant One-Dimensional Cellular Structure. - Rajesh Kumar; F. Gail Gray (ICDCS, 1984)

Parallel Computer Architectures and Problem Solving Strategies for the Consistent Labeling Problem. - Jeanette Tyler McCall; Joseph G. Tront; F. Gail Gray; Robert M. Haralick; William M. McCormack (IEEE Trans. Computers, 1985)

Micro-operation Perturbations in Chip Level Fault Modeling. - Chien-Hung Chao; F. Gail Gray (DAC, 1988)

Reconfiguring fault-tolerant two-dimensional array architectures. - Nathaniel J. Davis IV; F. Gail Gray; Joseph A. Wegner; Shannon E. Lawson; Vinay Murthy; Tennis S. White (IEEE Micro, 1994)

Efficient approaches to testing VHDL DSP models. - James R. Armstrong; Geoff Frank; F. Gail Gray (J. VLSI Signal Process., 1996)

A goal tree based high-level test planning system for DSP real number models. - Morris Lin; James R. Armstrong; F. Gail Gray (ITC, 1998)

VHDL modeling and model testing for DSP applications. - James R. Armstrong; F. Gail Gray; Meng-Wei Lin (IEEE Trans. Ind. Electron., 1999)

A Multi-Language Goal-Tree Based Functional Test Planning System. - Rajneesh Mahajan; Ramesh Govindarajulu; James R. Armstrong; F. Gail Gray (ITC, 2002)