The design of two easily-testable VLSI array multipliers. - F. Joel Ferguson; John Paul Shen (IEEE Symposium on Computer Arithmetic, 1983)

Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. - Wojciech Maly; F. Joel Ferguson; John Paul Shen (ITC, 1984)

The Design of Easily Tastabel VLSI Array Multipliers. - John Paul Shen; F. Joel Ferguson (IEEE Trans. Computers, 1984)

Inductive Fault Analysis of MOS Integrated Circuits. - John Paul Shen; Wojciech Maly; F. Joel Ferguson (IEEE Des. Test, 1985)

Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis. - John Paul Shen; F. Joel Ferguson (ITC, 1988)

Book Review: Logic Design Principles by Edward J. McCluskey: Prentice-Hall Publishers, Englewood Cliffs, New Jersey, 549 pp., $39.95. - F. Joel Ferguson (SIGARCH Comput. Archit. News, 1988)

A CMOS fault extractor for inductive fault analysis. - F. Joel Ferguson; John Paul Shen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Microprocessor Interfacing and the 68000: Peripherals and systems: Clements, A Wiley and Sons Ltd, Chichester, UK (1989) £39.95 pp 446. - F. Joel Ferguson (Microprocess. Microsystems, 1989)

Testing for parametric faults in static CMOS circuits. - F. Joel Ferguson; Martin Taylor; Tracy Larrabee (ITC, 1990)

Detection of multiple faults in MOS circuits. - F. Joel Ferguson (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Test Pattern Generation for Realistic Bridge Faults in CMOS ICs. - F. Joel Ferguson; Tracy Larrabee (ITC, 1991)

Test pattern generation for current testable faults in static CMOS circuits. - F. Joel Ferguson; Tracy Larrabee (VTS, 1991)

On the effectiveness of simultaneous self-test techniques. - Peter A. Johnson 002; F. Joel Ferguson (VTS, 1992)

Physical design for testability for bridges in CMOS circuits. - F. Joel Ferguson (VTS, 1993)

Carafe: an inductive fault analysis tool for CMOS VLSI circuits. - Alvin Jee; F. Joel Ferguson (VTS, 1993)

A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT. - Richard McGowen; F. Joel Ferguson (EDAC-ETC-EUROASIC, 1994)

Testing CMOS Logic Gates for Realistic Shorts. - Brian Chess; Anthony Freitas; F. Joel Ferguson; Tracy Larrabee (ITC, 1994)

Defect Classes - An Overdue Paradigm for CMOS IC. - Charles F. Hawkins; Jerry M. Soden; Alan W. Righter; F. Joel Ferguson (ITC, 1994)

Eliminating undetectable shorts between horizontal wires during channel routing. - Richard McGowen; F. Joel Ferguson (VTS, 1994)

Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks. - Haluk Konuk; F. Joel Ferguson; Tracy Larrabee (DAC, 1995)

Diagnosis of realistic bridging faults with single stuck-at information. - Brian Chess; David B. Lavo; F. Joel Ferguson; Tracy Larrabee (ICCAD, 1995)

Maximum Likelihood Estimation for Yield Analysis. - F. Joel Ferguson; Jianlin Yu (DFT, 1996)

An unexpected factor in testing for CMOS opens: the die surface. - Haluk Konuk; F. Joel Ferguson (VTS, 1996)

Detection of Multiple Faults in Two-Dimensional ILAs. - Martine D. F. Schlag; F. Joel Ferguson (IEEE Trans. Computers, 1996)

Charge-based fault simulation for CMOS network breaks. - Haluk Konuk; F. Joel Ferguson; Tracy Larrabee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits. - Haluk Konuk; F. Joel Ferguson (ITC, 1997)

Bridging Fault Diagnosis in the Absence of Physical Information. - David B. Lavo; Tracy Larrabee; F. Joel Ferguson; Brian Chess; Jayashree Saxena; Kenneth M. Butler (ITC, 1997)

Incorporating Physical Design-for-Test into Routing. - Richard McGowen; F. Joel Ferguson (ITC, 1997)

A methodolgy for characterizing cell testability. - Alvin Jee; F. Joel Ferguson (VTS, 1997)

Cache RAM inductive fault analysis with fab defect modeling. - T. M. Mak; Debika Bhattacharya; Cheryl Prunty; Bob Roeder; Nermine Ramadan; F. Joel Ferguson; Jianlin Yu (ITC, 1998)

On applying non-classical defect models to automated diagnosis. - Jayashree Saxena; Kenneth M. Butler; Hari Balachandran; David B. Lavo; Tracy Larrabee; F. Joel Ferguson; Brian Chess (ITC, 1998)

A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric. - Douglas Williams; F. Joel Ferguson; Tracy Larrabee (VTS, 1998)

Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits. - Haluk Konuk; F. Joel Ferguson (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Diagnosing realistic bridging faults with single stuck-at information. - David B. Lavo; Brian Chess; Tracy Larrabee; F. Joel Ferguson (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Checking sequence generation for asynchronous sequential elements. - Sezer Gören 001; F. Joel Ferguson (ITC, 1999)

Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test. - Michael A. Margolese; F. Joel Ferguson (VTS, 1999)

A Systematic DFT Procedure for Library Cells. - Jingjing Xu; Rahul Kundu; F. Joel Ferguson (VTS, 1999)

CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines. - Sezer Gören 001; F. Joel Ferguson (DATE, 2002)

Testing Finite State Machines Based on a Structural Coverage Metric . - Sezer Gören 001; F. Joel Ferguson (ITC, 2002)

Estimating detection probability of interconnect opens using stuck-at tests. - Shalini Ghosh; F. Joel Ferguson (ACM Great Lakes Symposium on VLSI, 2004)

Detection probabilities of interconnect breaks: an analysis. - Shalini Ghosh; F. Joel Ferguson (Integr., 2005)

Test sequence generation for controller verification and test with high coverage. - Sezer Gören 001; F. Joel Ferguson (ACM Trans. Design Autom. Electr. Syst., 2006)

On state reduction of incompletely specified finite state machines. - Sezer Gören 001; F. Joel Ferguson (Comput. Electr. Eng., 2007)