PACE: Fine-Grained Parallel Graph Reducion. - T. J. Reynolds; M. E. Waite; F. Z. Ieromnimon (ICPP (1), 1995)

A New Approach to the Design of a Highly-Parallel Computer. - M. E. Waite; T. J. Reynolds; F. Z. Ieromnimon (Parallel and Distributed Computing and Systems, 1995)

The Design and Simulation of the PACE Prototype Architecture. - F. Z. Ieromnimon; T. J. Reynolds; M. E. Waite (MASCOTS, 1996)

Parallel Graph Reduction with the PACE Architecture. - M. E. Waite; T. J. Reynolds; F. Z. Ieromnimon (PDP, 1996)

A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip. - Spyros Blionas; Kostas Masselos; Chrissavgi Dre; Christos Drosos; F. Z. Ieromnimon; T. Pagonis; Aristodemos Pneymatikakis; Anna Tatsaki; T. Trimis; A. Vontzalidis; Dimitris Metafas (FPL, 2002)