Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. - Philippe Flatresse; Bastien Giraud; Jean-Philippe Noel; Bertrand Pelloux-Prayer; Fabien Giner; Deepak-Kumar Arora; Franck Arnaud; Nicolas Planes; Julien Le Coz; Olivier Thomas; Sylvain Engels; Giorgio Cesana; et al. (ISSCC, 2013)

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI. - Fady Abouzeid; Audrey Bienfait; Kaya Can Akyel; Anis Feki; Sylvain Clerc; Lorenzo Ciampolini; Fabien Giner; Robin Wilson; Philippe Roche (IEEE J. Solid State Circuits, 2014)

Timing in-situ monitors: Implementation strategy and applications results. - Ahmed Benhassain; Florian Cacho; Vincent Huard; M. Saliva; Lorena Anghel; C. R. Parthasarathy; Abhishek Jain 003; Fabien Giner (CICC, 2015)

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. - Sylvain Clerc; Fady Abouzeid; Darayus Adil Patel; Jean-Marc Daveau; Cyril Bottoni; Lorenzo Ciampolini; Fabien Giner; David Meyer; Robin Wilson; Philippe Roche; Sylvie Naudet; Arnaud Virazel; et al. (ISQED, 2015)

28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications. - Rossella Ranica; Nicolas Planes; Vincent Huard; Olivier Weber; Daniel Noblet; Damien Croain; Fabien Giner; Sylvie Naudet; P. Mergault; S. Ibars; A. Villaret; Maryline Parra; et al. (VLSI Circuits, 2016)