Leakage energy reduction techniques in deep submicron cache memories: a comparative study. - Fabio Frustaci; Pasquale Corsonello; Stefania Perri; Giuseppe Cocorullo (ISCAS, 2006)

Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories. - Fabio Frustaci; Pasquale Corsonello; Stefania Perri; Giuseppe Cocorullo (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation. - Fabio Frustaci; Pasquale Corsonello; Stefania Perri; Giuseppe Cocorullo (PATMOS, 2008)

High-performance noise-tolerant circuit techniques for CMOS dynamic logic. - Fabio Frustaci; Pasquale Corsonello; Stefania Perri; Giuseppe Cocorullo (IET Circuits Devices Syst., 2008)

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. - Marco Lanuzza; Paolo Zicari; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (ARC, 2009)

A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder. - Fabio Frustaci; Marco Lanuzza (PATMOS, 2009)

Low-power split-path data-driven dynamic logic. - Fabio Frustaci; Marco Lanuzza; Paolo Zicari; Stefania Perri; Pasquale Corsonello (IET Circuits Devices Syst., 2009)

Designing High-Speed Adders in Power-Constrained Environments. - Fabio Frustaci; Marco Lanuzza; Paolo Zicari; Stefania Perri; Pasquale Corsonello (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A Low-Leakage Single-Ended 6T SRAM Cell. - Sohit Solanki; Fabio Frustaci; Pasquale Corsonello (ICETET, 2010)

A new low-power high-speed single-clock-cycle binary comparator. - Fabio Frustaci; Stefania Perri; Marco Lanuzza; Pasquale Corsonello (ISCAS, 2010)

Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. - Marco Lanuzza; Raffaele De Rose; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (ISVLSI, 2010)

Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. - Marco Lanuzza; Raffaele De Rose; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (PATMOS, 2010)

Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. - Marco Lanuzza; Paolo Zicari; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (ACM Trans. Reconfigurable Technol. Syst., 2010)

Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers. - Fabio Frustaci; Pasquale Corsonello; Massimo Alioto (ECCTD, 2011)

Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology. - Fabio Frustaci; Pasquale Corsonello; Massimo Alioto (ISCAS, 2011)

Tapered-Vth Approach for Energy-Efficient CMOS Buffers. - Fabio Frustaci; Massimo Alioto; Pasquale Corsonello (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Energy-efficient single-clock-cycle binary comparator. - Fabio Frustaci; Stefania Perri; Marco Lanuzza; Pasquale Corsonello (Int. J. Circuit Theory Appl., 2012)

Comparative analysis of yield optimized pulsed flip-flops. - Marco Lanuzza; Raffaele De Rose; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (Microelectron. Reliab., 2012)

Analytical Delay Model Considering Variability Effects in Subthreshold Domain. - Fabio Frustaci; Pasquale Corsonello; Stefania Perri (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A novel background subtraction method based on color invariants and grayscale levels. - Lorena Guachi; Giuseppe Cocorullo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (ICCST, 2014)

13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS. - Fabio Frustaci; Mahmood Khayatzadeh; David T. Blaauw; Dennis Sylvester; Massimo Alioto (ISSCC, 2014)

Designing Dynamic Carry Skip Adders: Analysis and Comparison. - Raffaele De Rose; Marco Lanuzza; Fabio Frustaci; Sohan Purohit (Circuits Syst. Signal Process., 2014)

Analyzing noise robustness of wide fan-in dynamic logic gates under process variations. - Fabio Frustaci; Marco Lanuzza; Stefania Perri; Pasquale Corsonello (Int. J. Circuit Theory Appl., 2014)

Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain. - Pasquale Corsonello; Fabio Frustaci; Marco Lanuzza; Stefania Perri (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology. - Pasquale Corsonello; Stefania Perri; Fabio Frustaci (ICCD, 2015)

Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse. - Fabio Frustaci; David T. Blaauw; Dennis Sylvester; Massimo Alioto (PATMOS, 2015)

A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS. - Mahmood Khayatzadeh; Fabio Frustaci; David T. Blaauw; Dennis Sylvester; Massimo Alioto (VLSIC, 2015)

Power supply noise in accurate delay model for the sub-threshold domain. - Pasquale Corsonello; Fabio Frustaci; Stefania Perri (Integr., 2015)

SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS. - Fabio Frustaci; Mahmood Khayatzadeh; David T. Blaauw; Dennis Sylvester; Massimo Alioto (IEEE J. Solid State Circuits, 2015)

Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology. - Pasquale Corsonello; Fabio Frustaci; Stefania Perri (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Design of efficient QCA multiplexers. - Giuseppe Cocorullo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (Int. J. Circuit Theory Appl., 2016)

An efficient hardware-oriented stereo matching algorithm. - Giuseppe Cocorullo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (Microprocess. Microsystems, 2016)

Approximate SRAMs With Dynamic Energy-Quality Management. - Fabio Frustaci; David T. Blaauw; Dennis Sylvester; Massimo Alioto (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Design of Efficient BCD Adders in Quantum-Dot Cellular Automata. - Giuseppe Cocorullo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems. - Fanny Spagnolo; Stefania Perri; Fabio Frustaci; Pasquale Corsonello (ICECS, 2018)

Designing Fast Convolutional Engines for Deep Learning Applications. - Fanny Spagnolo; Stefania Perri; Fabio Frustaci; Pasquale Corsonello (ICECS, 2018)

Design of Real-Time FPGA-based Embedded System for Stereo Vision. - Stefania Perri; Fabio Frustaci; Fanny Spagnolo; Pasquale Corsonello (ISCAS, 2018)

Multimodal background subtraction for high-performance embedded systems. - Giuseppe Cocorullo; Pasquale Corsonello; Fabio Frustaci; Lorena-de-los-Angeles Guachi-Guachi; Stefania Perri (J. Real Time Image Process., 2019)

Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation. - Fabio Frustaci; Stefania Perri; Pasquale Corsonello; Massimo Alioto (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs. - Fanny Spagnolo; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (ICECS, 2020)

Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip. - Fanny Spagnolo; Stefania Perri; Fabio Frustaci; Pasquale Corsonello (MECO, 2020)

Parallel architecture of power-of-two multipliers for FPGAs. - Stefania Perri; Fanny Spagnolo; Fabio Frustaci; Pasquale Corsonello (IET Circuits Devices Syst., 2020)

Stereo vision architecture for heterogeneous systems-on-chip. - Stefania Perri; Fabio Frustaci; Fanny Spagnolo; Pasquale Corsonello (J. Real Time Image Process., 2020)

Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation. - Fabio Frustaci; Stefania Perri; Pasquale Corsonello; Massimo Alioto (IEEE Trans. Circuits Syst., 2020)

Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA. - Stefania Perri; Fanny Spagnolo; Fabio Frustaci; Pasquale Corsonello (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An FPGA-Based Hardware Accelerator for the k-Nearest Neighbor Algorithm Implementation in Wearable Embedded Systems. - Antonio Borelli; Fanny Spagnolo; Raffaele Gravina; Fabio Frustaci (AII, 2022)

Designing Low-Power and High-Speed FPGA-Based Binary Decision Tree Hardware Accelerators. - Roman Huzyuk; Fanny Spagnolo; Fabio Frustaci (AII, 2022)

Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes. - Fabio Frustaci; Fanny Spagnolo; Stefania Perri; Giuseppe Cocorullo; Pasquale Corsonello (Sensors, 2022)

Multibit Full Comparator Logic in Quantum-Dot Cellular Automata. - Stefania Perri; Fanny Spagnolo; Fabio Frustaci; Pasquale Corsonello (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Design of Approximate Bilateral Filters for Image Denoising on FPGAs. - Fanny Spagnolo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (IEEE Access, 2023)

A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers. - Fabio Frustaci; Fanny Spagnolo; Stefania Perri; Pasquale Corsonello (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

HW/SW Codesign for Approximation-Aware Binary Neural Networks. - Abhilasha Dave; Fabio Frustaci; Fanny Spagnolo; Mikail Yayla; Jian-Jia Chen; Hussam Amrouch (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Design of Leading Zero Counters on FPGAs. - Stefania Perri; Fanny Spagnolo; Fabio Frustaci; Pasquale Corsonello (IEEE Embed. Syst. Lett., 2023)

Unlocking Efficiency in BNNs: Global by Local Thresholding for Analog-Based HW Accelerators. - Mikail Yayla; Fabio Frustaci; Fanny Spagnolo; Jian-Jia Chen; Hussam Amrouch (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

KIT: Kernel Isotropic Transformation of Bilateral Filters for Image Denoising on FPGA. - Fanny Spagnolo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (FPL, 2024)

COCOWEARS: A framework for COntinuum COmputing WEARable Systems. - Gianluca Aloi; Fabio Frustaci; Raffaele Gravina; Antonio Guerrieri; Gianvito Pio; Claudio Savaglio (ISM, 2024)

Efficient implementation of signed multipliers on FPGAs. - Fanny Spagnolo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (Comput. Electr. Eng., 2024)

An explainable embedded neural system for on-board ship detection from optical satellite imagery. - Cosimo Ieracitano; Nadia Mammone; Fanny Spagnolo; Fabio Frustaci; Stefania Perri; Pasquale Corsonello; Francesco Carlo Morabito (Eng. Appl. Artif. Intell., 2024)

Approximate bilateral filters for real-time and low-energy imaging applications on FPGAs. - Fanny Spagnolo; Pasquale Corsonello; Fabio Frustaci; Stefania Perri (J. Supercomput., 2024)

Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization. - Fanny Spagnolo; Stefania Perri; Massimo Vatalaro; Fabio Frustaci; Felice Crupi; Pasquale Corsonello (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations. - Fabio Frustaci; Fanny Spagnolo; Pasquale Corsonello; Stefania Perri (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Leveraging Highly Approximated Multipliers in DNN Inference. - Georgios Zervakis 001; Fabio Frustaci; Ourania Spantidi; Iraklis Anagnostopoulos; Hussam Amrouch; Jörg Henkel (IEEE Access, 2025)