A high throughput CAVLC hardware architecture with parallel coefficients processing for HDTV H.264/AVC enconding. - Fábio Luís Livi Ramos; Bruno Zatt; Thaísa Leal da Silva; Altamiro Amadeu Susin; Sergio Bampi (ICECS, 2010)

Low-power hardware design for the HEVC Binary Arithmetic Encoder targeting 8K videos. - Fábio Luís Livi Ramos; Jones Goebel; Bruno Zatt; Marcelo Schiavon Porto; Sergio Bampi (SBCCI, 2016)

Low-power HEVC binarizer architecture for the CABAC block targeting UHD video processing. - Camila de Matos Alonso; Fábio Luís Livi Ramos; Bruno Zatt; Marcelo Schiavon Porto; Sergio Bampi (SBCCI, 2017)

Low-power multi-size HEVC DCT architecture proposal for QFHD video processing. - Luana Vieira Martinez Bonatto; Fábio Luís Livi Ramos; Bruno Zatt; Marcelo Schiavon Porto; Sergio Bampi (SBCCI, 2017)

Novel multiple bypass bins scheme for low-power UHD video processing HEVC binary arithmetic encoder architecture. - Fábio Luís Livi Ramos; Bruno Zatt; Marcelo Schiavon Porto; Sergio Bampi (SBCCI, 2017)

HEVC Residual Syntax Elements Generation Architecture for High-Throughput CABAC Design. - Alessandro Via Piana Saggiorato; Fábio Luís Livi Ramos; Bruno Zatt; Marcelo Schiavon Porto; Sergio Bampi (ICECS, 2018)

High-Throughput Binary Arithmetic Encoder using Multiple-Bypass Bins Processing for HEVC CABAC. - Fábio Luís Livi Ramos; Bruno Zatt; Marcelo Schiavon Porto; Sergio Bampi (ISCAS, 2018)

Residual Syntax Elements Analysis and Design Targeting High-Throughput HEVC CABAC. - Fábio Luís Livi Ramos; Alessandro Via Piana Saggiorato; Bruno Zatt; Marcelo Schiavon Porto; Sergio Bampi (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Energy-Throughput Configurable Design for Video Processing Binary Arithmetic Encoder. - Fábio Luís Livi Ramos; Bruno Zatt; Marcelo Schiavon Porto; Sergio Bampi (IEEE Trans. Circuits Syst. Video Technol., 2021)

Power-Throughput Trade-off Analysis for a Novel Multi-Boolean AV1 Arithmetic Encoder Design. - Tulio Pereira Bitencourt; Fábio Luís Livi Ramos; Sergio Bampi (PCS, 2022)

Area and Power Efficient 8K Real-Time Design for AV1 Arithmetic Decoding. - Jiovana Sousa Gomes; Tulio Pereira Bitencourt; Sergio Bampi; Fábio Luís Livi Ramos (PCS, 2022)

Power-Saving 8K Real-Time AV1 Arithmetic Encoder Architecture. - Tulio Pereira Bitencourt; Fábio Luís Livi Ramos; Sergio Bampi (IEEE Des. Test, 2022)

Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder. - Jiovana Sousa Gomes; Tulio Pereira Bitencourt; Sergio Bampi; Fábio Luís Livi Ramos (IEEE Des. Test, 2022)

Analysis of AV1 Arithmetic Decoder Design Space with a Novel Multi-Boolean Approach. - Jiovana Sousa Gomes; Tulio Pereira Bitencourt; Sergio Bampi; Fábio Luís Livi Ramos (LASCAS, 2023)

AV1 Residual Syntax Elements Assessment and Efficient VLSI Architecture. - Jiovana Sousa Gomes; Rodrigo N. Wuerdig; Fábio Luís Livi Ramos; Sergio Bampi (SBCCI, 2023)

Statistical Analysis of VVC Residual and Entropy Coding aiming Efficient Hardware Design. - Gabriel Bitencourt Cardoso; Daniel Felipe Tomm; Jiovana Sousa Gomes; Rodrigo N. Wuerdig; Sergio Bampi; Fábio Luís Livi Ramos (LASCAS, 2024)

High-Performance Binary Arithmetic Encoder with Multiple Bypass Bin Scheme for VVC CABAC. - Vinícius Martins Faria; Jiovana Sousa Gomes; Sergio Bampi; Fábio Luís Livi Ramos (LASCAS, 2025)

End-to-End Neural Video Compression: A Review. - Jiovana Sousa Gomes; Mateus Grellert; Fábio Luís Livi Ramos; Sergio Bampi (IEEE Open J. Circuits Syst., 2025)

Hardware accelerator for VVC/H.266 residual syntax elements: a unified and resource-efficient architecture. - Gabriel Bitencourt Cardoso; Heitor Mauro Chavez Huarachi; Daniel Felipe Tomm; Jiovana Sousa Gomes; Rodrigo N. Wuerdig; Marcelo Romero de Moraes; Sergio Bampi; Fábio Luís Livi Ramos (J. Real Time Image Process., 2025)