A SiGe bipolar VCO for backhaul E-band communication systems. - Fabio Padovan; Marc Tiebout; Koen L. R. Mertens; Andrea Bevilacqua; Andrea Neviani (ESSCIRC, 2012)

A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS. - Fabio Padovan; Andrea Bevilacqua; Andrea Neviani (ESSCIRC, 2014)

A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation. - Fabio Padovan; Marc Tiebout; Andrea Neviani; Andrea Bevilacqua (ESSCIRC, 2015)

Design of Low-Noise K-Band SiGe Bipolar VCOs: Theory and Implementation. - Fabio Padovan; Marc Tiebout; Koen L. R. Mertens; Andrea Bevilacqua; Andrea Neviani (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers. - Fabio Padovan; Marc Tiebout; Andrea Neviani; Andrea Bevilacqua (ESSCIRC, 2016)

A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation. - Fabio Padovan; Marc Tiebout; Andrea Neviani; Andrea Bevilacqua (IEEE J. Solid State Circuits, 2016)

A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS. - Stefano Brenna; Fabio Padovan; Andrea Neviani; Andrea Bevilacqua; Andrea Bonfanti; Andrea L. Lacaita (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset. - Fabio Boscolo; Fabio Padovan; Fabio Quadrelli; Marc Tiebout; Andrea Neviani; Andrea Bevilacqua (ESSCIRC, 2017)

A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations. - Fabio Padovan; Fabio Quadrelli; Matteo Bassi; Marc Tiebout; Andrea Bevilacqua (ISSCC, 2018)

On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators. - Alessandro Franceschin; Fabio Padovan; Roberto Nonis; Andrea Bevilacqua (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS. - Matteo Bassi; Giovanni Boi; Fabio Padovan; Jonas Fritzin; Stefano Di Martino; Daniel Knauder; Andrea Bevilacqua (ESSCIRC, 2019)

A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion. - Alessandro Franceschin; Pietro Andreani; Fabio Padovan; Matteo Bassi; Roberto Nonis; Andrea Bevilacqua (ESSCIRC, 2019)

A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects. - Alessandro Franceschin; Pietro Andreani; Fabio Padovan; Matteo Bassi; Andrea Bevilacqua (IEEE J. Solid State Circuits, 2020)

A 22-31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS. - Davide Manente; Fabio Quadrelli; Fabio Padovan; Matteo Bassi; Andrea Mazzanti; Andrea Bevilacqua (ESSCIRC, 2021)

A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS. - Agata Iesurum; Davide Manente; Fabio Padovan; Matteo Bassi; Andrea Bevilacqua (ESSCIRC, 2022)

A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications. - Fabio Quadrelli; Davide Manente; David Seebacher; Fabio Padovan; Matteo Bassi; Andrea Mazzanti; Andrea Bevilacqua (IEEE J. Solid State Circuits, 2022)

A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise. - Lorenzo Tomasin; Pietro Andreani; Giovanni Boi; Fabio Padovan; Andrea Bevilacqua (IEEE J. Solid State Circuits, 2022)

A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures. - Davide Manente; Fabio Quadrelli; Fabio Padovan; Matteo Bassi; Andrea Mazzanti; Andrea Bevilacqua (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs. - Agata Iesurum; Davide Manente; Fabio Padovan; Matteo Bassi; Andrea Bevilacqua (IEEE J. Solid State Circuits, 2024)