A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications. - Fady Abouzeid; Sylvain Clerc; Fabian Firmin; Marc Renaudin; Gilles Sicard (ISLPED, 2009)

A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform. - Sylvain Clerc; Fady Abouzeid; Fabrice Argoud; Abhay Kumar 005; Rajesh Kumar; Philippe Roche (ICECS, 2011)

40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications. - Fady Abouzeid; Sylvain Clerc; Fabian Firmin; Marc Renaudin; Tiempo Sas; Gilles Sicard (ACM Trans. Design Autom. Electr. Syst., 2011)

28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder. - Fady Abouzeid; Sylvain Clerc; Bertrand Pelloux-Prayer; Fabrice Argoud; Philippe Roche (ESSCIRC, 2012)

A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance. - Sylvain Clerc; Fady Abouzeid; Gilles Gasiot; David Gauthier; Philippe Roche (ESSCIRC, 2012)

A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance. - Sylvain Clerc; Fady Abouzeid; Gilles Gasiot; David Gauthier; Dimitri Soussan; Philippe Roche (ICICDT, 2012)

Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. - Edith Beigné; Alexandre Valentian; Bastien Giraud; Olivier Thomas; Thomas Benoist; Yvain Thonnart; Serge Bernard; Guillaume Moritz; Olivier Billoint; Y. Maneglia; Philippe Flatresse; Jean-Philippe Noel; et al. (DATE, 2013)

Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI. - Fady Abouzeid; Audrey Bienfait; Kaya Can Akyel; Sylvain Clerc; Lorenzo Ciampolini; Philippe Roche (ESSCIRC, 2013)

27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. - Robin Wilson; Edith Beigné; Philippe Flatresse; Alexandre Valentian; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; Anuj Grover; et al. (ISSCC, 2014)

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI. - Fady Abouzeid; Audrey Bienfait; Kaya Can Akyel; Anis Feki; Sylvain Clerc; Lorenzo Ciampolini; Fabien Giner; Robin Wilson; Philippe Roche (IEEE J. Solid State Circuits, 2014)

28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. - Fady Abouzeid; Sylvain Clerc; Cyril Bottoni; Benjamin Coeffic; Jean-Marc Daveau; Damien Croain; Gilles Gasiot; Dimitri Soussan; Philippe Roche (ESSCIRC, 2015)

Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test. - Cyril Bottoni; Benjamin Coeffic; Jean-Marc Daveau; Gilles Gasiot; Fady Abouzeid; Sylvain Clerc; Lirida A. B. Naviner; Philippe Roche (IRPS, 2015)

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. - Sylvain Clerc; Fady Abouzeid; Darayus Adil Patel; Jean-Marc Daveau; Cyril Bottoni; Lorenzo Ciampolini; Fabien Giner; David Meyer; Robin Wilson; Philippe Roche; Sylvie Naudet; Arnaud Virazel; et al. (ISQED, 2015)

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. - Sylvain Clerc; Mehdi Saligane; Fady Abouzeid; Martin Cochet; Jean-Marc Daveau; Cyril Bottoni; David Bol; Julien De Vos; Dominique Zamora; Benjamin Coeffic; Dimitri Soussan; Damien Croain; et al. (ISSCC, 2015)

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. - Edith Beigné; Alexandre Valentian; Ivan Miro Panades; Robin Wilson; Philippe Flatresse; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; et al. (IEEE J. Solid State Circuits, 2015)

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Fady Abouzeid; et al. (COOL Chips, 2016)

30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation. - Fady Abouzeid; Christophe Bernicot; Sylvain Clerc; Jean-Marc Daveau; Gilles Gasiot; Daniel Noblet; Dimitri Soussan; Philippe Roche (ESSCIRC, 2016)

A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking. - Martin Cochet; Sylvain Clerc; Guenole Lallement; Fady Abouzeid; Philippe Roche; Jean-Luc Autran (A-SSCC, 2017)

A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI. - Guenole Lallement; Fady Abouzeid; Martin Cochet; Jean-Marc Daveau; Philippe Roche; Jean-Luc Autran (ESSCIRC, 2017)

A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI. - Guenole Lallement; Fady Abouzeid; Thierry Di Gilio; Philippe Roche; Jean-Luc Autran (A-SSCC, 2018)

Q-Learning-based Adaptive Power Management for IoT System-on-Chips with Embedded Power States. - Yvan Debizet; Guénolé Lallement; Fady Abouzeid; Philippe Roche; Jean-Luc Autran (ISCAS, 2018)

A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI. - Guenole Lallement; Fady Abouzeid; Martin Cochet; Jean-Marc Daveau; Philippe Roche; Jean-Luc Autran (IEEE J. Solid State Circuits, 2018)

FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip. - Sébastien Thomet; Serge De Paoli; Jean-Marc Daveau; Valérie Bertin; Fady Abouzeid; Philippe Roche; Fakhreddine Ghaffari; Olivier Romain (DFT, 2021)

IEEE 1838 compliant scan encryption and integrity for 2.5/3D ICs. - Juan Suzano; Antoine Chastand; Emanuele Valea; Giorgio Di Natale; Anthony Philippe; Fady Abouzeid; Philippe Roche (ETS, 2024)

On Hardware Security and Trust for Chiplet-Based 2.5D and 3D ICs: Challenges and Innovations. - Juan Suzano; Fady Abouzeid; Giorgio Di Natale; Anthony Philippe; Philippe Roche (IEEE Access, 2024)

Dose Effects and Mitigation in 28nm FD-SOI Advanced Interface Bus Chiplet Interconnect. - Antoine Rouget; Fady Abouzeid; Adrian Evans; Victor Malherbe; Aleksandra Chumakova; Philippe Roche; Fabien Clermidy (IOLTS, 2025)