HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on FPGAs: (Abstract Only). - Fady Hussein; Luka Daoud; Nader Rafla 001 (FPGA, 2018)

Real-time Bitstream Decompression Scheme for FPGAs Reconfiguration. - Luka Daoud; Fady Hussein; Nader Rafla 001 (MWSCAS, 2018)

Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS). - Luka Daoud; Fady Hussein; Nader Rafla 001 (CATA, 2019)

A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA. - Fady Hussein; Luka Daoud; Nader Rafla 001 (Microprocess. Microsystems, 2020)