An extendable global clock high-speed binary counter compatible to the FPGA CLBs. - Sarang Kazeminia; Maryam Ghafoorzadeh; Faeze Noruzpur (MIXDES, 2017)

A new fast rail-to-rail continuous-time common-mode feedback circuit. - Sina Mahdavi; Faeze Noruzpur; Esmaii Ghadimi; Tohid Moradi Khanshan (MIXDES, 2017)

A novel APS pixel level rearrangement to increase the fill factor and SNR in 0.35μm CMOS technology. - Ali Baradaran Rezaeii; Faeze Noruzpur; Sina Mahdavi (MIXDES, 2017)

A New Semi-Digital Low Power Low Jitter and Fast PLL in 0.18μm Technology. - Faeze Noruzpur; Sina Mahdavi; Maryam Poreh; Shima Tayyeb Ghasemi (MIXDES, 2018)