19.6 voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS System. - Fahim U. Rahman; Visvesh S. Sathe 001 (ISSCC, 2016)

A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. - Xun Sun; Sung Kim; Fahim ur Rahman; Venkata Rajesh Pamula 001; Xi Li; Naveen John; Visvesh S. Sathe 001 (ISSCC, 2018)

An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS. - Rajesh Pamula 001; Xun Sun; Sung Kim; Fahim ur Rahman; Baosen Zhang; Visvesh S. Sathe 001 (VLSI Circuits, 2018)

An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor. - Fahim ur Rahman; Sung Kim; Naveen John; Roshan Kumar; Xi Li; Rajesh Pamula 001; Keith A. Bowman; Visvesh S. Sathe 001 (VLSI Circuits, 2018)

Quasi-Resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking System for Dynamic Voltage-Frequency Scaling Systems. - Fahim U. Rahman; Visvesh Sathe 001 (IEEE J. Solid State Circuits, 2018)

Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS. - Fahim ur Rahman; Rajesh Pamula 001; Akshat Boora; Xun Sun; Visvesh Sathe 001 (ISSCC, 2019)

A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains. - Fahim ur Rahman; Sung Kim; Naveen John; Roshan Kumar; Xi Li; Rajesh Pamula 001; Keith A. Bowman; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2019)

A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation. - Fahim ur Rahman; Greg Taylor; Visvesh Sathe 001 (IEEE J. Solid State Circuits, 2019)

An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor. - Xun Sun; Fahim ur Rahman; Venkata Rajesh Pamula 001; Sung Kim; Xi Li; Naveen John; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2019)

Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS. - Fahim ur Rahman; Rajesh Pamula 001; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2020)