TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm. - Jianfei Wang 003; Chen Yang 005; Fahong Zhang 002; Yishuo Meng; Yang Su 003 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

An Efficient and Scalable FHE-Based PDQ Scheme: Utilizing FFT to Design a Low Multiplication Depth Large-Integer Comparison Algorithm. - Fahong Zhang 002; Chen Yang 005; Rui Zong; Xinran Zheng; Jianfei Wang 003; Yishuo Meng (IEEE Trans. Inf. Forensics Secur., 2024)

A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm. - Jianfei Wang 003; Chen Yang 005; Fahong Zhang 002; Yishuo Meng; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture. - Jianfei Wang 003; Chen Yang 005; Fahong Zhang 002; Jia Hou; Yishuo Meng; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data. - Jianfei Wang 003; Jia Hou; Fahong Zhang 002; Yishuo Meng; Yang Su 003; Chen Yang 005 (ASP-DAC, 2025)

An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm. - Jianfei Wang 003; Jia Hou; Fahong Zhang 002; Yishuo Meng; Yang Su 003; Chen Yang 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption. - Jianfei Wang 003; Chen Yang 005; Jia Hou; Fahong Zhang 002; Yishuo Meng; Yang Su 003; Leibo Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Reconfigurable and Area-Efficient Polynomial Multiplier Using a Novel In-Place Constant-Geometry NTT/INTT and Conflict-Free Memory Mapping Scheme. - Jianfei Wang 003; Chen Yang 005; Yishuo Meng; Fahong Zhang 002; Jia Hou; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline. - Jia Hou; Jianfei Wang 003; Yishuo Meng; Fahong Zhang 002; Yang Su 003; Chen Yang 005 (IEEE Trans. Very Large Scale Integr. Syst., 2025)