An Adaptive On-Line HW/SW Partitioning for Soft Real Time Reconfigurable Systems. - Fakhreddine Ghaffari; Michel Auguin; Mohamed Abid; Maher Benjemaa (DSD, 2005)

An efficient on-line Approach for on-chip HW/SW partitioner and scheduler. - Fakhreddine Ghaffari; Michel Auguin (ARCS Workshops, 2006)

Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures. - Fakhreddine Ghaffari; Michel Auguin; Mohamed Abid; Maher Ben Jemaa (Trans. High Perform. Embed. Archit. Compil., 2007)

Dynamic Adaptation of Hardware-Software Scheduling for Reconfigurable System-on-Chip. - Fakhreddine Ghaffari; Benoît Miramond; François Verdier (IEEE International Workshop on Rapid System Prototyping, 2008)

Run-Time HW/SW Scheduling of Data Flow Applications on Reconfigurable Architectures. - Fakhreddine Ghaffari; Benoît Miramond; François Verdier (EURASIP J. Embed. Syst., 2009)

Prediction performance method for dynamic task scheduling, case study: the OLLAF Architecture. - Ismail Ktata; Fakhreddine Ghaffari; Bertrand Granado; Mohamed Abid (IDT, 2010)

Novel Approach for Modeling Very Dynamic and Flexible Real Time Applications. - Ismail Ktata; Fakhreddine Ghaffari; Bertrand Granado; Mohamed Abid (ReCoSoC, 2010)

Dynamic Application Model for Scheduling with Uncertainty on Reconfigurable Architectures. - Ismail Ktata; Fakhreddine Ghaffari; Bertrand Granado; Mohamed Abid (Int. J. Reconfigurable Comput., 2011)

An efficient BER-based reliability method for SRAM-based FPGA. - Fouad Sahraoui; Fakhreddine Ghaffari; Mohamed El Amine Benkhelifa; Bertrand Granado (IDT, 2013)

An embedded implementation of home devices control system based on brain computer interface. - Kais Belwafi; Fakhreddine Ghaffari; Olivier Romain; Ridha Djemal (ICM, 2014)

Fast SRAM-FPGA fault injection platform based on dynamic partial reconfiguration. - Fakhreddine Ghaffari; Fouad Sahraoui; Mohamed El Amine Benkhelifa; Bertrand Granado; Marc Alexandre Kacou; Olivier Romain (ICM, 2014)

Reliability assessment of backward error recovery for SRAM-based FPGAs. - Fouad Sahraoui; Fakhreddine Ghaffari; Mohamed El Amine Benkhelifa; Bertrand Granado (IDT, 2014)

Context-aware resources placement for SRAM-based FPGA to minimize checkpoint/recovery overhead. - Fouad Sahraoui; Fakhreddine Ghaffari; Mohamed El Amine Benkhelifa; Bertrand Granado (ReConFig, 2014)

Efficient realization of probabilistic gradient descent bit flipping decoders. - Khoa Le; David Declercq; Fakhreddine Ghaffari; Christian Spagnol; Emanuel M. Popovici; Predrag Ivanis; Bane Vasic (ISCAS, 2015)

Analysis and implementation of on-the-fly stopping criteria for layered QC LDPC decoders. - Andrei Hera; Oana Boncalo; Constantina-Elena Gavriliu; Alexandru Amaricai; Valentin Savin; David Declercq; Fakhreddine Ghaffari (MIXDES, 2015)

FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding. - Truong Nguyen-Ly; Khoa Le; Fakhreddine Ghaffari; Alexandru Amaricai; Oana Boncalo; Valentin Savin; David Declercq (NEWCAS, 2015)

Online Adaptive Filters to Classify Left and Right Hand Motor Imagery. - Kais Belwafi; Ridha Djemal; Fakhreddine Ghaffari; Olivier Romain; Bouraoui Ouni; Sofien Gannouni (BIOSIGNALS, 2016)

Non-surjective finite alphabet iterative decoders. - Thien Truong Nguyen-Ly; Khoa Le; Valentin Savin; David Declercq; Fakhreddine Ghaffari; Oana Boncalo (ICC, 2016)

Influence of high-power electric motor on an FPGA used in the drive system of electric car. - Marc Alexandre Kacou; Fakhreddine Ghaffari; Olivier Romain; Bruno Condamin (IECON, 2016)

Noise-aided gradient descent bit-flipping decoders approaching maximum likelihood decoding. - David Declercq; Chris Winstead; Bane Vasic; Fakhreddine Ghaffari; Predrag Ivanis; Emmanuel Boutillon (ISTC, 2016)

Error rate estimation of a design implemented in an FPGA based on the operating conditions. - Marc Alexandre Kacou; Fakhreddine Ghaffari; Olivier Romain; Bruno Condamin (EWDTS, 2017)

Multi-Mode Low-Latency Software-Defined Error Correction for Data Centers. - Fakhreddine Ghaffari; Ali Akoglu; Bane Vasic; David Declercq (ICCCN, 2017)

Efficient FPGA implementation of probabilistic gallager B LDPC decoder. - Fakhreddine Ghaffari; Burak Unal; Ali Akoglu; Khoa Le; David Declercq; Bane Vasic (ICECS, 2017)

FPGA static timing analysis enhancement based on real operating conditions. - Marc Alexandre Kacou; Fakhreddine Ghaffari; Olivier Romain; Bruno Condamin (IECON, 2017)

Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders. - Khoa Le; Fakhreddine Ghaffari; David Declercq; Bane Vasic (ISCAS, 2017)

Analysis and implementation of resource efficient probabilistic Gallager B LDPC decoder. - Burak Unal; Fakhreddine Ghaffari; Ali Akoglu; David Declercq; Bane Vasic (NEWCAS, 2017)

Probabilistic model of AFDX frames reception for end system backlog assessment. - Yohan Baga; Morgane Richaud; Fakhreddine Ghaffari; Etienne Zante; David Declercq; Michael Nahmiyace (SIES, 2017)

Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping. - Khoa Le; Fakhreddine Ghaffari; David Declercq; Bane Vasic (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Hardware/Software Prototype of EEG-based BCI System for Home Device Control. - Kais Belwafi; Fakhreddine Ghaffari; Ridha Djemal; Olivier Romain (J. Signal Process. Syst., 2017)

On the Use of Hard-Decision LDPC Decoders on MLC NAND Flash Memory. - Khoa Le; Fakhreddine Ghaffari (SSD, 2018)

Probabilistic Gradient Descent Bit-Flipping Decoders for Flash Memory Channels. - Fakhreddine Ghaffari; Bane Vasic (ISCAS, 2018)

Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. - Khoa Le; Fakhreddine Ghaffari; Lounis Kessal; David Declercq; Valentin Savin; Oana Boncalo (ISCAS, 2018)

Recent Advances on Stochastic and Noise Enhanced Methods in Error Correction Decoders. - Chris Winstead; Tasnuva Tithi; Emmanuel Boutillon; Fakhreddine Ghaffari (ISTC, 2018)

On the use of Probabilistic Parallel Bit-Flipping decoder for the storage systems. - Khoa Le; Fakhreddine Ghaffari; David Declercq (MWSCAS, 2018)

An Imprecise Stopping Criterion Based on In-Between Layers Partial Syndromes. - David Declercq; Valentin Savin; Oana Boncalo; Fakhreddine Ghaffari (IEEE Commun. Lett., 2018)

Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. - Khoa Le; David Declercq; Fakhreddine Ghaffari; Lounis Kessal; Oana Boncalo; Valentin Savin (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders. - Burak Unal; Ali Akoglu; Fakhreddine Ghaffari; Bane Vasic (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders. - Thien Truong Nguyen-Ly; Valentin Savin; Khoa Le; David Declercq; Fakhreddine Ghaffari; Oana Boncalo (IEEE Trans. Very Large Scale Integr. Syst., 2018)

An Enhanced Offset Min-Sum decoder for 5G LDPC Codes. - Hangxuan Cui; Khoa LeTrung; Fakhreddine Ghaffari; David Declercq; Jun Lin 001; Zhongfeng Wang 001 (APCC, 2019)

Reliability Enhancement for Multi-level Cell NAND Flash Memory Using Error Asymmetry. - Duc-Phuc Nguyen; Khoa LeTrung; Fakhreddine Ghaffari; David Declercq (APCC, 2019)

An Adaptation of Min-Sum Decoder for 5G Low-Density Parity-Check Codes. - Khoa LeTrung; Fakhreddine Ghaffari; David Declercq (ISCAS, 2019)

A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes. - Hangxuan Cui; Khoa Le; Fakhreddine Ghaffari; David Declercq; Jun Lin 001; Zhongfeng Wang 001 (ISCIT, 2019)

Performance Enhancement of Polar Codes in Multi-level Cell NAND Flash Memories using Systematic Encoding. - Duc-Phuc Nguyen; Khoa Le; Fakhreddine Ghaffari; David Declercq (ISCIT, 2019)

The Probabilistic Finite Alphabet Iterative Decoder for Low-Density Parity-Check Codes. - Fakhreddine Ghaffari; Khoa Le; David Declercq (NEWCAS, 2019)

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes. - Khoa Le; Fakhreddine Ghaffari; Lounis Kessal; David Declercq; Emmanuel Boutillon; Chris Winstead; Bane Vasic (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip. - Sébastien Thomet; Serge De Paoli; Jean-Marc Daveau; Valérie Bertin; Fady Abouzeid; Philippe Roche; Fakhreddine Ghaffari; Olivier Romain (DFT, 2021)

An Enhanced Check-Node Architecture for 5G New Radio LDPC Decoders. - Fakhreddine Ghaffari; Khoa Le (ICECS, 2021)

Reduced Complexity of a Successive Cancellation Based Decoder for NB-Polar Codes. - F. Cochachin; Laura Luzzi; Fakhreddine Ghaffari (ISTC, 2021)

Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes. - Hangxuan Cui; Fakhreddine Ghaffari; Khoa Le; David Declercq; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Layout-based reliability analysis of openMSP430 register file under external radiations. - Vivek Bansal; Otmane Aït Mohamed; Fakhreddine Ghaffari (ICM, 2023)

Optimal Sensor Set for Decoding Motor Imagery from EEG. - Arnau Dillen; Fakhreddine Ghaffari; Olivier Romain; Bram Vanderborght; Romain Meeusen; Bart Roelands; Kevin De Pauw (NER, 2023)

The Syndrome Bit Flipping Algorithm for LDPC Codes. - Emmanuel Boutillon; Chris Winstead; Fakhreddine Ghaffari (IEEE Commun. Lett., 2023)

Enhancing Deep Learning-Based Epileptic Seizure Detection with Generative AI Techniques. - Hamza Bouallagui; Hamza Chniter; Fakhreddine Ghaffari; Olivier Romain (ICM, 2024)

User Evaluation of a Shared Robot Control System Combining BCI and Eye Tracking in a Portable Augmented Reality User Interface. - Arnau Dillen; Mohsen Omidi; Fakhreddine Ghaffari; Olivier Romain; Bram Vanderborght; Bart Roelands; Ann Nowé; Kevin De Pauw (Sensors, 2024)