VLSI Architecture and Implementation for Speech Recognizer Based on Discriminative Bayesian Neural Network. - Jhing-Fa Wang; Jia-Ching Wang; An-Nan Suen; Chung-Hsien Wu 001; Fan-Min Li (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

VLSI design of dual-mode Viterbi/turbo decoder for 3GPP. - Kai Huang; Fan-Min Li; Pei-Ling Shen; An-Yeu Wu (ISCAS (2), 2004)

Multiple-Translation Spotting for Mandarin-Taiwanese Speech-to-Speech Translation. - Jhing-Fa Wang; Shun-Chieh Lin; Hsueh-Wei Yang; Fan-Min Li (Int. J. Comput. Linguistics Chin. Lang. Process., 2004)

A New Early Termination Scheme of Iterative Turbo Decoding Using Decoding Threshold. - Fan-Min Li; Cheng-Hung Lin; An-Yeu Wu (SiPS, 2006)

High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems. - Chih-Hsiu Lin; An-Yeu Wu; Fan-Min Li (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

On the New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold. - Fan-Min Li; An-Yeu Wu (IEEE Trans. Signal Process., 2007)

Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel. - Fan-Min Li; Cheng-Hung Lin; An-Yeu Wu (IEEE Trans. Very Large Scale Integr. Syst., 2008)