Fan Yang
Orcid: 0000-0003-2164-8175Affiliations:
- Fudan University, State Key Lab of ASIC & System, School of Microelectronics, Shanghai, China
According to our database1,
Fan Yang
authored at least 119 papers
between 2006 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental Variation.
ACM Trans. Design Autom. Electr. Syst., January, 2024
2023
High-Level Topology Synthesis Method for Δ-Σ Modulators via Bi-Level Bayesian Optimization.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
Unleashing the Power of Graph Spectral Sparsification for Power Grid Analysis via Incomplete Cholesky Factorization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
Proc. ACM Interact. Mob. Wearable Ubiquitous Technol., September, 2023
ACM Trans. Design Autom. Electr. Syst., July, 2023
ACM Trans. Design Autom. Electr. Syst., March, 2023
A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid.
ACM Trans. Design Autom. Electr. Syst., January, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
Train Faster, Perform Better: Modular Adaptive Training in Over-Parameterized Models.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the Eleventh International Conference on Learning Representations, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Automated and Agile Design of Layout Hotspot Detector via Neural Architecture Search.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
ACM Trans. Design Autom. Electr. Syst., 2022
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proc. ACM Interact. Mob. Wearable Ubiquitous Technol., 2022
Do Smart Glasses Dream of Sentimental Visions?: Deep Emotionship Analysis for Eyewear Devices.
Proc. ACM Interact. Mob. Wearable Ubiquitous Technol., 2022
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022
NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
SAT-based Scheduling Algorithm for High-level Synthesis Considering Resource Sharing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the Tenth International Conference on Learning Representations, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Topology Optimization of Operational Amplifier in Continuous Space via Graph Embedding.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble.
CoRR, 2021
Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State Compression.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Efficient High-Level Synthesis of Approximate Computing Circuits via Multi-fidelity Modeling.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
Improved Low-Power Cost-Effective DCT Implementation Based on Markov Random Field and Stochastic Logic.
IEEE Trans. Circuits Syst. Video Technol., 2020
Neural Comput. Appl., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition.
IEEE Trans. Very Large Scale Integr. Syst., 2019
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access via Data Reuse.
ACM Trans. Reconfigurable Technol. Syst., 2019
Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method.
IEEE J. Solid State Circuits, 2018
Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design.
Proceedings of the 35th International Conference on Machine Learning, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Improved Tangent Space-Based Distance Metric for Lithographic Hotspot Classification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Efficient spectral graph sparsification via Krylov-subspace based spectral perturbation analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Fast compressive sensing reconstruction algorithm on FPGA using Orthogonal Matching Pursuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Efficient performance modeling of analog integrated circuits via kernel density based sparse regression.
Proceedings of the 53rd Annual Design Automation Conference, 2016
An efficient trajectory-based algorithm for model order reduction of nonlinear systems via localized projection and global interpolation.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
MOS Table Models for Fast and Accurate Simulation of Analog and Mixed-Signal Circuits Using Efficient Oscillation-Diminishing Interpolations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
A parallel sparse linear system solver for large-scale circuit simulation based on Schur Complement.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuits.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Improved tangent space based distance metric for accurate lithographic hotspot classification.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Full-Spectrum Spatial-Temporal Dynamic Thermal Analysis for Nanometer-Scale Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Stochastic Non-homogeneous Arnoldi Method for Analysis of On-Chip Power Grid Networks under Process Variations.
IEICE Trans. Electron., 2011
2010
A Wavelet-Collocation-Based Trajectory Piecewise-Linear Algorithm for Time-Domain Model-Order Reduction of Nonlinear Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
NHAR: A non-homogeneous Arnoldi method for fast simulation of RCL circuits with a large number of ports.
Int. J. Circuit Theory Appl., 2010
An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
A Modified Nested Sparse Grid Based Adaptive Stochastic Collocation Method for Statistical Static Timing Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Proceedings of the 46th Design Automation Conference, 2009
2007
RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006