Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2008)

An Enhanced Logic BIST Architecture for Online Testing. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (IOLTS, 2008)

Detection of Internal Stuck-open Faults in Scan Chains. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2008)

On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (VTS, 2008)

Detectability of internal bridging faults in scan chains. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (ASP-DAC, 2009)

Improving the Detectability of Resistive Open Faults in Scan Cells. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2009)

Testing of latch based embedded arrays using scan tests. - Fan Yang 060; Sreejit Chakravarty (ITC, 2010)

Silicon evaluation of faster than at-speed transition delay tests. - Sreejit Chakravarty; Narendra Devta-Prasanna; Arun Gunda; Junxia Ma; Fan Yang 060; H. Guo; R. Lai; D. Li (VTS, 2012)

A novel method for fast identification of peak current during test. - Wei Zhao 010; Sreejit Chakravarty; Junxia Ma; Narendra Devta-Prasanna; Fan Yang 060; Mohammad Tehranipoor (VTS, 2012)

Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay Tests. - Fan Yang 060; Sreejit Chakravarty; Arun Gunda; Nicole Wu; Jianyu Ning (ATS, 2014)