Fan Ye

According to our database1, Fan Ye authored at least 76 papers between 2007 and 2019.

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Bibliography

2019
A Novel Nauta Transconductor for Ultra-Wideband gm-C Filter with Temperature Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Capacitively-Degenerated High-Linearity Dynamic Amplifier using a Real-Time Gain Detection Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Simultaneous STF and NTF Estimation in CTΔΣ Modulators with ARMA-Model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 13-bit 180-MS/s SAR ADC with Efficient Capacitor-Mismatch Estimation and Dither Enhancement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier.
IEEE Trans. on Circuits and Systems, 2018

An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration.
Microelectronics Journal, 2018

Low Power Low Noise Amplifier with DC Offset Correction at 1 V Supply Voltage for Ultrasound Imaging Systems.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A Third-order Band-pass Fully-passive Noise-Shaping Modulator Based on a Time-interleaved SAR ADC.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A 12-Bit ENOB 8MHz BW Noise-Shaping SAR ADC Using High-Speed Switches.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching.
IEEE Trans. VLSI Syst., 2017

A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Smartly Searching Multimedia Data in Heterogeneous Mobile Ad Hoc Networks.
Proceedings of the Fuzzy Systems and Data Mining III, 2017

A stacked-packaged 16-channel ADC for ultrasound application.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 12bit asynchronous SAR-incremental sub-range ADC.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 0.87 mW 7MHz-BW 76dB-SNDR passive noise-shaping modulator based on a SAR ADC.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

An input buffer for 12bit 2GS/s ADC.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A proved dither-injection method for memory effect in double sampling pipelined ADC.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2015
An ARMA-Model-Based NTF Estimation on Continuous-Time ΔΣ Modulators.
IEEE Trans. on Circuits and Systems, 2015

A high power-efficient LVDS output driver with adjustable feed-forward capacitor compensation.
IEICE Electronic Express, 2015

Switch-back based on charge equalization switching technique for SAR ADC.
IEICE Electronic Express, 2015

A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system.
Proceedings of the ESSCIRC Conference 2015, 2015

A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

I/Q imbalance estimation in OFDM systems.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A 100MS/s 5bit fully digital flash ADC with standard cells.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

LVDS transmitter with optimized high power-efficiency 8: 1 MUX.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A 42fJ 8-bit 1.0-GS/s folding and interpolating ADC with 1GHz signal bandwidth.
IEICE Electronic Express, 2014

A 7 bit 1 GS/s pipelined folding and interpolating ADC with coarse-stage-free joint encoding.
IEICE Electronic Express, 2014

A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Carrier Frequency Offset and I/Q Imbalance Compensation for MB-OFDM Based UWB System.
Wireless Personal Communications, 2013

A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1.
IEEE Trans. on Circuits and Systems, 2013

A mixed sample-time error calibration technique in time-interleaved ADCs.
IEICE Electronic Express, 2013

A 7.9-fJ/conversion-step 8-b 400-MS/s 2-b-per-cycle SAR ADC with A preset capacitive DAC.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A DLL based low-phase-noise clock multiplier with offset-tolerant PFD.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Automatic gain control algorithm with high-speed and double closed-loop in UWB system.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Low-complexity synchronizer used in DC-OFDM UWB system.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A novel joint estimation and compensation algorithm for non-idealities of analog front-end in DC-OFDM system.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Comments on "Estimation of Carrier Frequency Offset With I/Q Mismatch Using Pseudo-Offset Injection in OFDM Systems".
IEEE Trans. on Circuits and Systems, 2012

Output-dependent delay cancellation technique for high-accuracy current-steering DACs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
A Parallel Early-Pruned K-Best MIMO Signal Detector Up to 1.9Gb/s.
Wireless Personal Communications, 2011

Nyquist-rate time-interleaved current-steering DAC with dynamic channel matching.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

Class-AB CMOS buffer with floating class-AB control.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Area efficient LDPC decoder design for parallel layered decoding.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A 12-bit 50-MSPS SHA-less opamp-sharing Analog-to-Digital converter in 65nm CMOS.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- muhboxm CMOS Technology.
IEEE Trans. on Circuits and Systems, 2010

Joint estimation and compensation for front-end imperfection in MB-OFDM UWB systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 0.22 pJ/step subsampling ADC with fast input-tracking sampling and simplified opamp sharing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A sideband-suppressed low-power synthesizer for 14-band dual-carrier MB-OFDM UWB transceivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A Novel Operational Amplifier for Low-voltage Low-power SC Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Design of Highly-Parallel, 2.2Gbps Throughput Signal Detector for MIMO Systems.
Proceedings of IEEE International Conference on Communications, 2008

2007
A Novel Synchronizer for OFDM-based UWB System on New Preamble Design.
Proceedings of the IEEE 18th International Symposium on Personal, 2007

Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication System.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


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