Fan Ye
Orcid: 0000-0002-1089-1498Affiliations:
- Fudan University, State-Key Laboratory of ASIC and Systems, Shanghai, China
According to our database1,
Fan Ye
authored at least 140 papers
between 2006 and 2023.
Collaborative distances:
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Bibliography
2023
28-nm CMOS Ultrasound AFE With Split Attenuation for Optimizing Gain-Range, Noise, and Area.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Low-Noise Low-Power Ultrasound AFE With Continuous TGC Built in Both TIA and Beamformer.
IEEE Trans. Biomed. Circuits Syst., October, 2023
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
A 400-MS/s 12-bit Voltage-Time Hybrid ADC with a Ping-Pong SAR TDC for Speed Enhancement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Three-stage Analog Low-Frequency Drift Calibration and DC Offset Correction Circuit for Ultrasonic AFE.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Broadband LMS-based Band-split Crosstalk Cancellation Method for Ultrasound Systems.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
A Branch-Gain-Balanced LNA Based on Voltage- Controlled Resistor Feedback and Shared CMFB Amplifier.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
A Single-Channel 1.25-GS/s 11-bit Pipelined ADC with Robust Floating-Powered Ring Amplifier and First-Order Gain Error Calibration.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
The Research of the Consistency Control Under the Condition of Time-Lag of Isomerism AUV Group Communication.
Proceedings of the Bio-Inspired Computing: Theories and Applications, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET.
IEEE Access, 2021
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS.
IEEE Access, 2021
Additive Neural Network Based Static and Dynamic Distortion Modeling for Prior-Knowledge-Free Nyquist ADC Characterization.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
A Novel Ring Amplifier with Low Common-Mode Voltage Variation and Noise Reduction Using Floating Power Technique.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
A Hardware-Efficient Calibrator for SAR-Pipelined ADCs with a Layer-based Sharing Neural Network.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration.
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
A High Linearity Bootstrapped Switch with Leakage Current Suppressed for GS/s Sampling Rate ADC.
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Partially Binarized and Fixed Neural Network Based Calibrator for SAR-Pipelined ADCs Achieving 95.0-dB SFDR.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
A 5-bit High-Linearity, Binary-Recombination-Redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
A Wide-Range 12b 150MS/s P-SAR ADC with Open-Loop Residue Amplifier for Ultrasound AFE.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
A 12-bit SAR ADC Using Pseudo-Dynamic Weighting C-DAC for Capacitor Error Calibration.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
An Area-Power-Efficient AFE with NS-SAR ADC For High-Frequency Ultrasound Applications.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
A Low Power Reference Voltage Buffer and High Density Unit capacitor in a 12b 200MS/s SAR ADC.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
A Calibration Scheme for Nonlinearity of the SAR-Pipelined ADCs Based on a Shared Neural Network.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic.
Microelectron. J., 2019
A Ring Amplifier Based Current Feedback Continuous Time PGA for High Frequency Ultrasound Applications.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
A Band-Pass Noise-Shaping Modulator Using the Error-Feedback Structure on a 10-bit SAR ADC.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
A 20MHz Bandwidth Band-Pass Noise-Shaping SAR ADC With OPAMP Sharing Switched-Capacitor Filter.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
A Novel Nauta Transconductor for Ultra-Wideband gm-C Filter with Temperature Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Capacitively-Degenerated High-Linearity Dynamic Amplifier using a Real-Time Gain Detection Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 13-bit 180-MS/s SAR ADC with Efficient Capacitor-Mismatch Estimation and Dither Enhancement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration.
Microelectron. J., 2018
Low Power Low Noise Amplifier with DC Offset Correction at 1 V Supply Voltage for Ultrasound Imaging Systems.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
A Third-order Band-pass Fully-passive Noise-Shaping Modulator Based on a Time-interleaved SAR ADC.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
High speed digital ELD compensation with hybrid thermometer coding in CT ΔΣ modulators.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the Fuzzy Systems and Data Mining III, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
IEICE Electron. Express, 2016
2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
A high power-efficient LVDS output driver with adjustable feed-forward capacitor compensation.
IEICE Electron. Express, 2015
IEICE Electron. Express, 2015
IEICE Electron. Express, 2015
A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system.
Proceedings of the ESSCIRC Conference 2015, 2015
A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
IEICE Electron. Express, 2014
A 7 bit 1 GS/s pipelined folding and interpolating ADC with <i>coarse-stage-free joint encoding</i>.
IEICE Electron. Express, 2014
A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Carrier Frequency Offset and I/Q Imbalance Compensation for MB-OFDM Based UWB System.
Wirel. Pers. Commun., 2013
A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEICE Electron. Express, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
A 7.9-fJ/conversion-step 8-b 400-MS/s 2-b-per-cycle SAR ADC with A preset capacitive DAC.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Automatic gain control algorithm with high-speed and double closed-loop in UWB system.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
A novel joint estimation and compensation algorithm for non-idealities of analog front-end in DC-OFDM system.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Comments on "Estimation of Carrier Frequency Offset With I/Q Mismatch Using Pseudo-Offset Injection in OFDM Systems".
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Carrier Frequency Offset estimation in the Presence of I/Q Mismatch for Wideband OFDM systems.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
A cancellation technique for output-dependent delay differences in high-accuracy DACs.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Output-dependent delay cancellation technique for high-accuracy current-steering DACs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
Wirel. Pers. Commun., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- muhboxm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A 0.22 pJ/step subsampling ADC with fast input-tracking sampling and simplified opamp sharing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A sideband-suppressed low-power synthesizer for 14-band dual-carrier MB-OFDM UWB transceivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend.
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
Proceedings of IEEE International Conference on Communications, 2008
2007
Proceedings of the IEEE 18th International Symposium on Personal, 2007
Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication System.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006