A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet. - Lu Ping; Ye Fan 001; Junyan Ren (ISCAS, 2006)

Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System. - Liang Liu 002; Junyan Ren; Xuejing Wang; Fan Ye 001 (ISCAS, 2007)

Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication System. - Zhuo Xu; Junyan Ren; Xuejing Wang; Fan Ye 001 (ISCAS, 2007)

A Novel Synchronizer for OFDM-based UWB System on New Preamble Design. - Xuejing Wang; Liang Liu 002; Fan Ye 001; Junyan Ren; Bo Hu (PIMRC, 2007)

Design of Highly-Parallel, 2.2Gbps Throughput Signal Detector for MIMO Systems. - Liang Liu 002; Xiaojing Ma 001; Fan Ye 001; Junyan Ren (ICC, 2008)

A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend. - Lei Luo; Kaihui Lin; Long Cheng; Liren Zhou; Fan Ye 001; Junyan Ren (ESSCIRC, 2009)

A Novel Operational Amplifier for Low-voltage Low-power SC Circuits. - Mingjun Fan; Junyan Ren; Yao Guo; Yuanwen Li; Fan Ye 001; Ning Li 007 (ISCAS, 2009)

A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator. - Ping Lu; Danfeng Chen; Fan Ye 001; Junyan Ren (SoCC, 2009)

A sideband-suppressed low-power synthesizer for 14-band dual-carrier MB-OFDM UWB transceivers. - Danfeng Chen; Haipeng Fu; Yunfeng Chen; Wei Li 038; Fan Ye 001; Ning Li 007; Junyan Ren (ISCAS, 2010)

A 0.22 pJ/step subsampling ADC with fast input-tracking sampling and simplified opamp sharing. - Guanghua Shu; Fan Ye 001; Yao Guo; Mingjun Fan; Junyan Ren; Jun Xu 011; Ning Li 007; Cheng Chen (ISCAS, 2010)

Joint estimation and compensation for front-end imperfection in MB-OFDM UWB systems. - Jun Zhou 002; Liang Liu 002; Fan Ye 001; Junyan Ren (ISCAS, 2010)

A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- muhboxm CMOS Technology. - Liang Liu 002; Fan Ye 001; Xiaojing Ma 001; Tong Zhang 002; Junyan Ren (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application. - Qianqian Ha; Fan Ye 001; Chixiao Chen; Xiaoshi Zhu; Mingshuo Wang; Yu-Jing Lin; Ning Li 007; Junyan Ren (ASICON, 2011)

A 12-bit 50-MSPS SHA-less opamp-sharing Analog-to-Digital converter in 65nm CMOS. - Chen Shu; Guanghua Shu; Jun Xu 011; Fan Ye 001; Junyan Ren (ASICON, 2011)

Area efficient LDPC decoder design for parallel layered decoding. - Yuan Yao; Fan Ye 001; Junyan Ren (ASICON, 2011)

Class-AB CMOS buffer with floating class-AB control. - Peng Zhang; Fan Ye 001; Junyan Ren (ASICON, 2011)

A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation. - Bei Yu; Chixiao Chen; Yu Zhu; Peng Zhang; Yiwen Zhang; Xiaoshi Zhu; Fan Ye 001; Junyan Ren (A-SSCC, 2011)

Nyquist-rate time-interleaved current-steering DAC with dynamic channel matching. - Long Cheng; Fan Ye 001; Hai-Feng Yang; Ning Li 007; Jun Xu 011; Junyan Ren (ISCAS, 2011)

A Parallel Early-Pruned K-Best MIMO Signal Detector Up to 1.9Gb/s. - Liang Liu 002; Junyan Ren; Xiaojing Ma 001; Fan Ye 001 (Wirel. Pers. Commun., 2011)

A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation. - Yiwen Zhang; Xiaoshi Zhu; Chixiao Chen; Fan Ye 001; Junyan Ren (APCCAS, 2012)

Output-dependent delay cancellation technique for high-accuracy current-steering DACs. - Long Cheng; Yu-Jing Lin; Fan Ye 001; Ning Li 007; Junyan Ren (ISCAS, 2012)

An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling. - Chixiao Chen; ShengChang Cai; Jialiang Xu; Xiaoshi Zhu; Fan Ye 001; Junyan Ren (MWSCAS, 2012)

A digitally calibrated current-steering DAC with current-splitting array. - Long Cheng; Chixiao Chen; Fan Ye 001; Ning Li 007; Junyan Ren (MWSCAS, 2012)

A cancellation technique for output-dependent delay differences in high-accuracy DACs. - Long Cheng; Yu-Jing Lin; Mingshuo Wang; Fan Ye 001; Ning Li 007; Junyan Ren (MWSCAS, 2012)

A 1.2 V 1.0-GS/s 8-bit Voltage-Buffer-Free Folding and interpolating ADC. - Mingshuo Wang; Tao Lin; Fan Ye 001; Ning Li 007; Junyan Ren (MWSCAS, 2012)

Carrier Frequency Offset estimation in the Presence of I/Q Mismatch for Wideband OFDM systems. - Xiaolong Wang; Yuankun Xue; Liang Liu 002; Fan Ye 001; Junyan Ren (MWSCAS, 2012)

Comments on "Estimation of Carrier Frequency Offset With I/Q Mismatch Using Pseudo-Offset Injection in OFDM Systems". - Xiaolong Wang; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique. - Yongzhen Chen; Chixiao Chen; Qiang Zhang; Fan Ye 001; Junyan Ren (ASICON, 2013)

A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator. - Zemin Feng; Chixiao Chen; Fan Ye 001; Jun Xu 011; Junyan Ren (ASICON, 2013)

A novel joint estimation and compensation algorithm for non-idealities of analog front-end in DC-OFDM system. - Jiasen Huang; Hao Chen; Junyan Ren; Fan Ye 001 (ASICON, 2013)

Low-complexity synchronizer used in DC-OFDM UWB system. - Bing Jing; Hao Chen; Fan Ye 001; Ning Li 007; Junyan Ren (ASICON, 2013)

Automatic gain control algorithm with high-speed and double closed-loop in UWB system. - Bing Jing; Yuankun Xue; Fan Ye 001; Ning Li 007; Junyan Ren (ASICON, 2013)

A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC. - Jian Mei; Jixuan Xiang; Huabin Chen; Fan Ye 001; Junyan Ren (ASICON, 2013)

A DLL based low-phase-noise clock multiplier with offset-tolerant PFD. - Yuwen Wang; Fan Ye 001; Junyan Ren (ASICON, 2013)

A 7.9-fJ/conversion-step 8-b 400-MS/s 2-b-per-cycle SAR ADC with A preset capacitive DAC. - Jixuan Xiang; Jian Mei; Hao Chang; Fan Ye 001 (ASICON, 2013)

Power efficient SAR ADC with optimized settling technique. - Weiru Gu; Hao Zhou 008; Tao Lin; Zhenyu Wang; Fan Ye 001; Junyan Ren (MWSCAS, 2013)

A mixed sample-time error calibration technique in time-interleaved ADCs. - Bei Yu; Chixiao Chen; Fan Ye 001; Junyan Ren (IEICE Electron. Express, 2013)

A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1. - Zhenyu Wang; Mingshuo Wang; Weiru Gu; Chixiao Chen; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Carrier Frequency Offset and I/Q Imbalance Compensation for MB-OFDM Based UWB System. - Liang Liu 002; Junyan Ren; Jun Zhou 002; Fan Ye 001 (Wirel. Pers. Commun., 2013)

Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis. - Yuankun Xue; Zhiliang Qian; Paul Bogdan; Fan Ye 001; Chi-Ying Tsui (DAC, 2014)

A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier. - Chixiao Chen; Zemin Feng; Huabin Chen; Mingshuo Wang; Jun Xu 011; Fan Ye 001; Junyan Ren (ISCAS, 2014)

A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators. - Guoxian Dai; Chixiao Chen; Shunli Ma; Fan Ye 001; Junyan Ren (ISCAS, 2014)

A 7 bit 1 GS/s pipelined folding and interpolating ADC with coarse-stage-free joint encoding. - Mingshuo Wang; Li Lin; Fan Ye 001; Junyan Ren (IEICE Electron. Express, 2014)

A 42fJ 8-bit 1.0-GS/s folding and interpolating ADC with 1GHz signal bandwidth. - Mingshuo Wang; Fan Ye 001; Wei Li 038; Junyan Ren (IEICE Electron. Express, 2014)

A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL. - Fazhi An; Shunli Ma; Qian Chen; Guangyao Zhou; Fan Ye 001; Junyan Ren (ASICON, 2015)

A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology. - Qian Chen; Fazhi An; Guangyao Zhou; Shunli Ma; Fan Ye 001; Junyan Ren (ASICON, 2015)

LVDS transmitter with optimized high power-efficiency 8: 1 MUX. - Yuan Su; Yimin Wu; Qiang Zhang; Xuerong Zhou; Fan Ye 001; Junyan Ren (ASICON, 2015)

100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array. - Jingjing Wang; Rongjin Xu; Chixiao Chen; Fan Ye 001; Jun Xu 011; Junyan Ren (ASICON, 2015)

An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units. - Weizhen Wang; Hao Zhou 008; Fan Ye 001; Junyan Ren (ASICON, 2015)

A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network. - Rongjin Xu; Yongzhen Chen; Mingshuo Wang; Ning Li 007; Fan Ye 001; Junyan Ren (ASICON, 2015)

A 100MS/s 5bit fully digital flash ADC with standard cells. - Xiangyan Xue; Xuerong Zhou; Fan Ye 001; Junyan Ren (ASICON, 2015)

I/Q imbalance estimation in OFDM systems. - Xuerong Zhou; Xiangyan Xue; Fan Ye 001; Junyan Ren (ASICON, 2015)

A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS. - Guangyao Zhou; Shunli Ma; Fazhi An; Ning Li 007; Fan Ye 001; Junyan Ren (ASICON, 2015)

A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. - Shunli Ma; Guangyao Zhou; Jianbing Jiang; Chixiao Chen; Yongzhen Chen; Fan Ye 001; Junyan Ren (ESSCIRC, 2015)

A 270-MS/s 6-b SAR ADC with preamplifier sharing and self-locking comparators. - Chixiao Chen; Jixuan Xiang; Jiang Fan; Xu Jun; Ye Fan 001; Junyan Ren (IEICE Electron. Express, 2015)

Switch-back based on charge equalization switching technique for SAR ADC. - Weiru Gu; Fan Ye 001; Junyan Ren (IEICE Electron. Express, 2015)

A high power-efficient LVDS output driver with adjustable feed-forward capacitor compensation. - Yuan Su; Fan Ye 001; Junyan Ren (IEICE Electron. Express, 2015)

An ARMA-Model-Based NTF Estimation on Continuous-Time ΔΣ Modulators. - Chixiao Chen; Zemin Feng; Jun Xu 011; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A self-adaptive write driver with fast termination of step-up pulse for ReRAM. - Jianguo Yang; Xiaoyong Xue; Juan Xu; Fan Ye 001; Yinyin Lin; Ryan Huang; Qingtian Zou; Jingang Wu (IEICE Electron. Express, 2016)

A proved dither-injection method for memory effect in double sampling pipelined ADC. - Fubiao Cao; Yongzhen Chen; Yuefeng Cao; Fan Ye 001; Junyan Ren (ASICON, 2017)

An input buffer for 12bit 2GS/s ADC. - Fubiao Cao; Yongzhen Chen; Zhiyuan Dai; Fan Ye 001; Junyan Ren (ASICON, 2017)

A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error. - Xiaoqing Chen; Fan Ye 001; Junyan Ren (ASICON, 2017)

A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs. - Yongzhen Chen; Yimin Wu; Fubiao Cao; Fan Ye 001; Junyan Ren (ASICON, 2017)

A 0.87 mW 7MHz-BW 76dB-SNDR passive noise-shaping modulator based on a SAR ADC. - Zhiyuan Dai; Hang Hu 003; Manxin Li; Fan Ye 001; Junyan Ren (ASICON, 2017)

A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique. - Hang Hu 003; Zhiyuan Dai; Manxin Li; Fan Ye 001; Junyan Ren (ASICON, 2017)

A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation. - Hang Hu 003; Manxin Li; Zhiyuan Dai; Fan Ye 001; Junyan Ren (ASICON, 2017)

A 12bit asynchronous SAR-incremental sub-range ADC. - Manxin Li; Hang Hu 003; Zhiyuan Dai; Fan Ye 001; Junyan Ren (ASICON, 2017)

A stacked-packaged 16-channel ADC for ultrasound application. - Yimin Wu; Yongzhen Chen; Manxin Li; Fan Ye 001; Junyan Ren (ASICON, 2017)

A clock interpolation structure using DLL for clock distribution in ADC. - Shijia Zhu; Yu Wang 167; Fan Ye 001; Jun Xu (ASICON, 2017)

Smartly Searching Multimedia Data in Heterogeneous Mobile Ad Hoc Networks. - Fan Ye 001; Zuobin Ying; Yiwen Zhang; Cheng Zheng (FSDM, 2017)

A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier. - Yongzhen Chen; Jingjing Wang; Hang Hu 003; Fan Ye 001; Junyan Ren (ISCAS, 2017)

High speed digital ELD compensation with hybrid thermometer coding in CT ΔΣ modulators. - Hang Hu 003; Zemin Feng; Chixiao Chen; Fan Ye 001; Junyan Ren (MWSCAS, 2017)

An improved ring amplifier with process- and supply voltage-insensitive dead-zone. - Yuefeng Cao; Yongzhen Chen; Tianli Zhang; Fan Ye 001; Junyan Ren (MWSCAS, 2017)

A 3.2-to-4.6 GHz fast-settling all-digital PLL with feed forward frequency presetting. - Tao Yang 022; Sichen Yu; Huixiang Han; Xiaolu Liu; Dashan Pan; Xi Tan 001; Na Yan; Fan Ye 001; Junyu Wang; Hao Min (IEICE Electron. Express, 2017)

Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{ mathrm {cm}}$ -Based Switching. - Dezhi Xing; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Fan Ye 001; Junyan Ren; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC. - Yuefeng Cao; Yongzhen Chen; Zhekan Ni; Fan Ye 001; Junyan Ren (APCCAS, 2018)

An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs. - Yuefeng Cao; Tianli Zhang; Yongzhen Chen; Fan Ye 001; Junyan Ren (ISCAS, 2018)

A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation. - Yongzhen Chen; Zhekan Ni; Yuefeng Cao; Fan Ye 001; Junyan Ren (ISCAS, 2018)

A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC. - Manxin Li; Yongzhen Chen; Fan Ye 001; Junyan Ren (ISCAS, 2018)

Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC. - Tianli Zhang; Yuefeng Cao; Fan Ye 001; Junyan Ren (ISCAS, 2018)

A 12-Bit ENOB 8MHz BW Noise-Shaping SAR ADC Using High-Speed Switches. - Zhiyuan Dai; Hang Hu 003; Yongzhen Chen; Fan Ye 001; Junyan Ren (MWSCAS, 2018)

A Third-order Band-pass Fully-passive Noise-Shaping Modulator Based on a Time-interleaved SAR ADC. - Zhiyuan Dai; Hang Hu 003; Yimin Wu; Fan Ye 001; Junyan Ren (MWSCAS, 2018)

Low Power Low Noise Amplifier with DC Offset Correction at 1 V Supply Voltage for Ultrasound Imaging Systems. - Longheng Luo; Yimin Wu; Jianguo Diao; Fan Ye 001; Junyan Ren (MWSCAS, 2018)

An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration. - Yongzhen Chen; Fan Ye 001; Junyan Ren (Microelectron. J., 2018)

A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier. - Yongzhen Chen; Jingjing Wang; Hang Hu 003; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 40Gb/s Low Power Transmitter with 2-tap FFE and 40: 1 MUX in 28nm CMOS Technology. - Wenbin He; Fan Ye 001; Junyan Ren (ASICON, 2019)

A Comparator-Reused Dynamic-Amplifier for Noise-Shaping SAR ADC. - Longheng Luo; Xingchen Shen; Jianguo Diao; Fan Ye 001; Junyan Ren (ASICON, 2019)

A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers. - Yuting Yao; Jipeng Wei; Manxin Li; Shunli Ma; Fan Ye 001; Junyan Ren (ASICON, 2019)

A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period. - Shumin Zhang; Yuefeng Cao; Fan Ye 001; Junyan Ren (ASICON, 2019)

A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps. - Yongzhen Chen; Xingchen Shen; Zhekan Ni; Jingchao Lan; Chixiao Chen; Fan Ye 001; Junyan Ren (ESSCIRC, 2019)

Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR. - Tianli Zhang; Yuefeng Cao; Shumin Zhang; Chixiao Chen; Fan Ye 001; Junyan Ren (ESSCIRC, 2019)

A 13-bit 180-MS/s SAR ADC with Efficient Capacitor-Mismatch Estimation and Dither Enhancement. - Fan Ye 001; Shuai Li 014; Min Zhu; Zhekan Ni; Junyan Ren (ISCAS, 2019)

Simultaneous STF and NTF Estimation in CTΔΣ Modulators with ARMA-Model. - Hang Hu 009; Calvin Y. Lee; Ahmed ElShater; Zhiyuan Dai; Fan Ye 001; Un-Ku Moon (ISCAS, 2019)

A Capacitively-Degenerated High-Linearity Dynamic Amplifier using a Real-Time Gain Detection Technique. - Longheng Luo; Yimin Wu; Jipeng Wei; Fan Ye 001; Junyan Ren (ISCAS, 2019)

A Novel Nauta Transconductor for Ultra-Wideband gm-C Filter with Temperature Calibration. - Jipeng Wei; Yuting Yao; Longheng Luo; Shunli Ma; Fan Ye 001; Junyan Ren (ISCAS, 2019)

Energy-Efficient Analog Frond-End Design for Ultrasound Imaging Applications. - Jianguo Diao; Shuai Li 014; Yimin Wu; Fan Ye 001; Jun Xu 019; Junyan Ren (MWSCAS, 2019)

A 20MHz Bandwidth Band-Pass Noise-Shaping SAR ADC With OPAMP Sharing Switched-Capacitor Filter. - Shuai Li 014; Jianguo Diao; Yimin Wu; Fan Ye 001; Junyan Ren (MWSCAS, 2019)

A Band-Pass Noise-Shaping Modulator Using the Error-Feedback Structure on a 10-bit SAR ADC. - Longheng Luo; Shuai Li 014; Jipeng Wei; Yimin Wu; Fan Ye 001; Junyan Ren (MWSCAS, 2019)

A Ring Amplifier Based Current Feedback Continuous Time PGA for High Frequency Ultrasound Applications. - Yimin Wu; Jingchao Lan; Shuai Li 014; Fan Ye 001; Junyan Ren (MWSCAS, 2019)

A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. - Zhekan Ni; Yongzhen Chen; Fan Ye 001; Junyan Ren (Microelectron. J., 2019)

A Calibration Scheme for Nonlinearity of the SAR-Pipelined ADCs Based on a Shared Neural Network. - Min Chen 036; Yimin Wu; Jingchao Lan; Fan Ye 001; Chixiao Chen; Junyan Ren (APCCAS, 2020)

A Low Power Reference Voltage Buffer and High Density Unit capacitor in a 12b 200MS/s SAR ADC. - Wenbin He; Ziwei Li; Fan Ye 001; Junyan Ren (APCCAS, 2020)

A Low-Power Low-Noise Dynamic Comparator With Latch-Embedding Floating Amplifier. - Ziwei Li; Wenbin He; Fan Ye 001; Junyan Ren (APCCAS, 2020)

A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems. - Yimin Wu; Jingchao Lan; Min Chen 036; Fan Ye 001; Junyan Ren (APCCAS, 2020)

An Area-Power-Efficient AFE with NS-SAR ADC For High-Frequency Ultrasound Applications. - Yimin Wu; Shuai Li 014; Longheng Luo; Fan Ye 001; Junyan Ren (APCCAS, 2020)

A 13 Bit 100 MS/s SAR ADC with 74.57 dB SNDR in 14-nm CMOS FinFET. - Yan Zheng; Fan Ye 001; Junyan Ren (ISCAS, 2020)

A Fast Response Reference Voltage Buffer for 12b 200MS/s SAR ADC. - Wenbin He; Fan Ye 001; Junyan Ren (MWSCAS, 2020)

A 12-bit SAR ADC Using Pseudo-Dynamic Weighting C-DAC for Capacitor Error Calibration. - Fan Ye 001; Junyan Ren (MWSCAS, 2020)

A High Linearity and Low Noise Anti-Aliasing Filter for ADCs. - Hao Chi; Jun Xu; Fan Ye 001; Junyan Ren (ASICON, 2021)

A Wide-Range 12b 150MS/s P-SAR ADC with Open-Loop Residue Amplifier for Ultrasound AFE. - Ziwei Li; Yutong Zhao; Guoyao Wu; Fan Ye 001; Junyan Ren (ASICON, 2021)

Advances in Continuous-time MASH ΔΣ Modulators. - Liang Qi 002; Xinyu Qin; Sai-Weng Sin; Chixiao Chen; Fan Ye 001; Guoyong Shi; Guoxing Wang (ASICON, 2021)

A Three-Stage Comparator with High Speed and Low Power. - Jingqi Wang; Fan Ye 001; Junyan Ren (ASICON, 2021)

A 5-bit High-Linearity, Binary-Recombination-Redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC. - Guoyao Wu; Ziwei Li; Yutong Zhao; Fan Ye 001; Junyan Ren (ASICON, 2021)

A 68.36 dB 12 bit 100MS/s SAR ADC with a low-noise comparator in 14-nm CMOS FinFet. - Yan Zheng; Jingchao Lan; Fan Ye 001; Junyan Ren (ASICON, 2021)

A Partially Binarized and Fixed Neural Network Based Calibrator for SAR-Pipelined ADCs Achieving 95.0-dB SFDR. - Min Chen 036; Yutong Zhao; Nuo Xu; Fan Ye 001; Junyan Ren (ISCAS, 2021)

An 11-Bit 500 MS/s Two-Step SAR ADC with Non-Attenuated Passive Residue Transfer. - Wenbin He; Fan Ye 001; Junyan Ren (ISCAS, 2021)

A High Linearity Bootstrapped Switch with Leakage Current Suppressed for GS/s Sampling Rate ADC. - Jingchao Lan; Yan Zheng; Yimin Wu; Min Chen 036; Fan Ye 001; Junyan Ren (ISOCC, 2021)

Resistive Degeneration Linearization Dynamic Residue Amplifiers for Pipelined ADCs. - Ziwei Li; Guoyao Wu; Yutong Zhao; Fan Ye 001; Junyan Ren (ISOCC, 2021)

Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration. - Danfeng Zhai; Chixiao Chen; Liang Qi 002; Fan Ye 001; Junyan Ren (ISOCC, 2021)

Self-coupled MASH Delta-Sigma Modulator with Zero Optimization. - Jingying Zhang; Yang Zhao; Mingyi Chen; Chixiao Chen; Fan Ye 001; Liang Qi 002 (ISOCC, 2021)

A Hardware-Efficient Calibrator for SAR-Pipelined ADCs with a Layer-based Sharing Neural Network. - Min Chen 036; Nuo Xu; Yutong Zhao; Fan Ye 001; Junyan Ren (MWSCAS, 2021)

A Novel Ring Amplifier with Low Common-Mode Voltage Variation and Noise Reduction Using Floating Power Technique. - Jingchao Lan; Yan Zheng; Yimin Wu; Fan Ye 001; Junyan Ren (MWSCAS, 2021)

Additive Neural Network Based Static and Dynamic Distortion Modeling for Prior-Knowledge-Free Nyquist ADC Characterization. - Danfeng Zhai; Peizhe Li; Jiushan Zhang; Chixiao Chen; Fan Ye 001; Junyan Ren (MWSCAS, 2021)

A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS. - Manxin Li; Yuting Yao; Biao Hu; Jipeng Wei; Yong Chen 005; Shunli Ma; Fan Ye 001; Junyan Ren (IEEE Access, 2021)

A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET. - Yan Zheng; Jingchao Lan; Fan Ye 001; Junyan Ren (IEEE Access, 2021)

A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS. - Yuefeng Cao; Shumin Zhang; Tianli Zhang; Yongzhen Chen; Yutong Zhao; Chixiao Chen; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Low Noise TIA with Continuous Time-Gain Compensation for Ultrasound Transducers. - Xinwei Yu; Fan Ye 001; Junyan Ren (APCCAS, 2022)

A 500-MS/s 9-Bit Time-Domain ADC Using a Nonbinary Successive Approximation TDC. - Yutong Zhao; Fan Ye 001; Junyan Ren (APCCAS, 2022)

A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration. - Jingchao Lan; Danfeng Zhai; Yongzhen Chen; Zhekan Ni; Xingchen Shen; Fan Ye 001; Junyan Ren (ISCAS, 2022)

A Single-Channel 1.25-GS/s 11-bit Pipelined ADC with Robust Floating-Powered Ring Amplifier and First-Order Gain Error Calibration. - Jingchao Lan; Yuxuan Zhang; Fan Ye 001; Junyan Ren (MWSCAS, 2022)

A Branch-Gain-Balanced LNA Based on Voltage- Controlled Resistor Feedback and Shared CMFB Amplifier. - Lulu Liu; Yimin Wu; Xinwei Yu; Fan Ye 001; Junyan Ren (MWSCAS, 2022)

A Broadband LMS-based Band-split Crosstalk Cancellation Method for Ultrasound Systems. - Wenhan Lu; Yimin Wu; Fan Ye 001; Junyan Ren (MWSCAS, 2022)

High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. - Danfeng Zhai; Wenning Jiang; Xinru Jia; Jingchao Lan; Mingqiang Guo; Sai-Weng Sin; Fan Ye 001; Qi Liu 010; Junyan Ren; Chixiao Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation. - Jingchao Lan; Yongzhen Chen; Xingchen Shen; Zhekan Ni; Yimin Wu; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Common Architecture for Digital Process of Ultrasonic Imaging System after AFE. - Chongzheng Fang; Chenhui Zhou; Fan Ye 001 (ASICON, 2023)

Periodic Analysis of Adaptive LMS Filter in TIADC. - Jiankun Li; Zepeng Lin; Fan Ye 001 (ASICON, 2023)

A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology. - Bingrong Lyu; Fan Ye 001; Junyan Ren (ASICON, 2023)

A Three-stage Analog Low-Frequency Drift Calibration and DC Offset Correction Circuit for Ultrasonic AFE. - Siqing Wu; Xinwei Yu; Xingtao Zhu; Fan Ye 001; Junyan Ren (ASICON, 2023)

A 400-MS/s 12-bit Voltage-Time Hybrid ADC with a Ping-Pong SAR TDC for Speed Enhancement. - Yutong Zhao; Yuguo Xiang; Fan Ye 001; Junyan Ren (ISCAS, 2023)

On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators. - Jingying Zhang; Sai-Weng Sin; Yan Liu 016; Fan Ye 001; Guoxing Wang; Maurits Ortmanns; Liang Qi 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order. - Kaiquan Chen; Biao Wang; Yan Liu 016; Fan Ye 001; Sai-Weng Sin; Guoxing Wang; Yong Lian 001; Liang Qi 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Low-Noise Low-Power Ultrasound AFE With Continuous TGC Built in Both TIA and Beamformer. - Xinwei Yu; Yan Wang 097; Fan Ye 001; Junyan Ren (IEEE Trans. Biomed. Circuits Syst., 2023)

28-nm CMOS Ultrasound AFE With Split Attenuation for Optimizing Gain-Range, Noise, and Area. - Xinwei Yu; Zhi Chen; Siqing Wu; Lulu Liu; Hao Chi; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Hardware-Implemented Calibration Based on Sinusoidal Fitting for Hybrid Pipeline ADC. - Yuguo Xiang; Yutong Zhao; Dayan Zhou; Danfeng Zhai; Junyan Ren; Fan Ye 001 (ISCAS, 2024)

An Effective Digital Calibration Method Based on Volterra Neural Network for Pipeline ADCs. - Yuguo Xiang; Danfeng Zhai; Junyan Ren; Fan Ye 001 (ISCAS, 2025)

A Comprehensive Digital Calibration for Pipelined ADCs Using Cascaded Nonlinearity Correction. - Yuguo Xiang; Dayan Zhou; Minjia Song; Danfeng Zhai; Jingchao Lan; Junyan Ren; Fan Ye 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)