A novel glitch reduction circuitry for binary-weighted DAC. - Fang-Ting Chou; Chia-Min Chen; Zong-Yi Chen; Chung-Chih Hung (APCCAS, 2014)

A 10-bit 250MS/s low-glitch binary-weighted digital-to-analog converter. - Fang-Ting Chou; Zong-Yi Chen; Chung-Chih Hung (SoCC, 2014)

A compact 12-bit DAC with novel bias scheme. - Fang-Ting Chou; Chung-Chih Hung (IEICE Electron. Express, 2014)

A novel 12-bit current-steering DAC with two reference currents. - Fang-Ting Chou; Zong-Yi Chen; Hsing-Chien Chu; Chung-Chih Hung (ISCAS, 2015)

Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC. - Fang-Ting Chou; Chung-Chih Hung (IEEE Trans. Very Large Scale Integr. Syst., 2016)