A 1.25-GS/s 12-bit inter-stage gain calibration-free pipelined ADC with gain-enhanced and current-biased ring amplifiers. - Fangning Song; Xuan Guo 003; Hanbo Jia; Jingyuan Xu; Wenhao Ren; Fangyuan Xu; Xinyu Liu 004 (Microelectron. J., 2026)