Compressive Spectrum Sensing Based on Sparse Sub-band Basis in Wireless Sensor Network. - Yu Wang; Jincheng Zhang; Quan Wang; Fangxu Lv; Kewei Chen (CWSN, 2014)

A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology. - Fangxu Lv; Xuqiang Zheng; Ziqiang Wang; Jianye Wang; Fule Li (ASICON, 2015)

A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS. - Xuqiang Zheng; Chun Zhang; Fangxu Lv; Feng Zhao 004; Shigang Yue; Ziqiang Wang; Fule Li; Zhihua Wang 001 (ESSCIRC, 2016)

Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology. - Fangxu Lv; Jianye Wang; Dengjie Wang; Yongcong Liu; Ziqiang Wang (ASICON, 2017)

A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS. - Xuqiang Zheng; Fangxu Lv; Feng Zhao 004; Shigang Yue; Chun Zhang; Ziqiang Wang; Fule Li; Hanjun Jiang; Zhihua Wang 001 (CICC, 2017)

A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS. - Xuqiang Zheng; Chun Zhang; Fangxu Lv; Feng Zhao 004; Shigang Yue; Ziqiang Wang; Fule Li; Hanjun Jiang; Zhihua Wang 001 (CICC, 2017)

An 8.5-12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes. - Yajun He; Ziqiang Wang; Han Liu; Fangxu Lv; Shuai Yuan 005; Chun Zhang; Zhihua Wang 001; Hanjun Jiang (MWSCAS, 2017)

A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology. - Fangxu Lv; Xuqiang Zheng; Shuai Yuan 005; Ziqiang Wang; Yajun He; Chun Zhang; Zhihua Wang 001; Jianye Wang (MWSCAS, 2017)

A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS. - Xuqiang Zheng; Chun Zhang; Fangxu Lv; Feng Zhao 004; Shuai Yuan 005; Shigang Yue; Ziqiang Wang; Fule Li; Zhihua Wang 001; Hanjun Jiang (IEEE J. Solid State Circuits, 2017)

A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications. - Fangxu Lv; Xuqiang Zheng; Feng Zhao 004; Jianye Wang; Shigang Yue; Ziqiang Wang; Weidong Cao 001; Yajun He; Chun Zhang; Hanjun Jiang; Zhihua Wang 001 (Microelectron. J., 2018)

A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS. - Hao Ding; Xuqiang Zheng; DanYu Wu; Lei Zhou 014; Jin Wu; Fangxu Lv; Jianye Wang; Xinyu Liu 004 (ESSCIRC, 2019)

A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology. - Dengjie Wang; Hong Chen 002; Wenhuan Luan; Xin Lin; Fangxu Lv; Ziqiang Wang; Hanjun Jiang; Chun Zhang; Zhihua Wang 001 (MWSCAS, 2019)

A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology. - Zhengbin Pang; Fangxu Lv; Weiping Tang; Mingche Lai; Kaile Guo; Yuxuan Wu; Tao Liu; Miaomiao Wu; Dechao Lu (ACA, 2020)

A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS. - Xuqiang Zheng; Hao Ding; Feng Zhao 004; DanYu Wu; Lei Zhou 014; Jin Wu; Fangxu Lv; Jianye Wang; Xinyu Liu 004 (IEEE J. Solid State Circuits, 2020)

Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators. - Xuqiang Zheng; Fangxu Lv; Lei Zhou 014; DanYu Wu; Jin Wu; Chun Zhang; Woogeun Rhee; Xinyu Liu 004 (IEEE J. Solid State Circuits, 2020)

A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface. - Geng Zhang 001; Fangxu Lv; Zhengbin Pang; Heming Wang; Dongbin Lv; Tao Liu; Jinwang Zhang (ASICON, 2021)

An Analytical Jitter Transfer Model for Mueller-Muller Clock and Data Recovery Circuits. - Tao Liu; Fangxu Lv; Bin Liang; Heming Wang; Jianye Wang; Miaomiao Wu (ASICON, 2021)

An Adaptive Equalization Algorithm for High Speed SerDes. - Miaomiao Wu; Zhengbin Pang; Fangxu Lv; Jianjun Shi; Heming Wang; Tao Liu; Dechao Lu; Zheng Wang (ASICON, 2021)

A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. - Mingche Lai; Geng Zhang 001; Fangxu Lv; Xuqiang Zheng; Heming Wang; Dongbin Lv; Chaolong Xu; Xingyun Qi (Microelectron. J., 2022)

A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks. - Mingche Lai; Fangxu Lv; Geng Zhang 001; Chaolong Xu (HPCC/DSS/SmartCity/DependSys, 2023)

Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications. - Qing Liu; Heming Wang; Fangxu Lv; Geng Zhang 001; Dongbin Lv (ICCEIC, 2023)

A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology. - Qiuyue Zhang; Xuqiang Zheng; Fangxu Lv; Zhaoyang Liu; Hua Xu; Weijie Li; Zhi Jin; Mingche Lai; Xinyu Liu (Microelectron. J., 2023)

A reduced complexity MLSD-based adaptive Duo-PAM4 detector in 28-nm CMOS for 56-Gb/s wireline receiver. - Chaolong Xu; Fangxu Lv; Mingche Lai; Zhang Luo; Xingyun Qi; Jiaqing Xu; Qiang Wang 006; Liquan Xiao; Cewen Liu; Hua Xu (A-SSCC, 2024)

An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM. - Yu He; Xuqiang Zhenq; Zedong Wang; Zunsong Yanq; Hua Xu; Fangxu Lv; Mingche Lai; Xinyu Liu (CICC, 2024)

FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver. - Chaolong Xu; Fangxu Lv; Zhengbin Pang; Liquan Xiao; Zhouhao Yang (ACM Great Lakes Symposium on VLSI, 2024)

A high speed and low BER dual-mode adaptive equalizer using hybrid parallel DFE. - Xiaoyue Hu; Fangxu Lv; Mingche Lai; Zhang Luo; Qiang Wang; Chaolong Xu; Ruotian Yin; Zhouhao Yang; Cewen Liu (IEICE Electron. Express, 2024)

A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process. - Wenchen Wang; Fangxu Lv; Zhengbin Pang; Heng Huang; Zhang Luo; Xingyun Qi; Jiaqing Xu; Geng Zhang 001; Kewei Xin; Chengzhuo Zhao (IEICE Electron. Express, 2024)

A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs. - Meng Li; Fangxu Lv; Mingche Lai; Xuqiang Zheng; Heng Huang; Xingyun Qi; Geng Zhang 001 (Microelectron. J., 2024)

A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface. - Bolin Ren; Fangxu Lv; Mingche Lai; Liquan Xiao; Geng Zhang 001; Xuqiang Zheng; Zhang Luo; Jiaqing Xu (Microelectron. J., 2024)

Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator. - Kewei Xin; Mingche Lai; Fangxu Lv; Xuqiang Zheng; Kaile Guo; Zhengbin Pang; Chaolong Xu; Geng Zhang 001; Wenchen Wang; Meng Li (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization. - Zhang Luo; Sichun Du; Zedi Zhang; Fangxu Lv; Qinghui Hong; Mingche Lai (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 100 Gb/s PAM4 receiver analog front-end with 33.1-dB boost in 28-nm CMOS process. - Qiuyue Zhang; Xuqiang Zheng; Fangxu Lv; Wenxiang Zhen; Mingche Lai; Zhi Jin; Xinyu Liu 004 (IEICE Electron. Express, 2025)

A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver. - Cewen Liu; Xingyun Qi; Fangxu Lv; Qiang Wang 006; Liquan Xiao; Xiaoyue Hu; Chaolong Xu; Zhouhao Yang; Meng Li; Mingche Lai (Microelectron. J., 2025)

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment. - Zedong Wang; Xuqiang Zheng; Yu He; Hua Xu; Sai Li; Zunsong Yang; Fangxu Lv; Mingche Lai; Xinyu Liu 004 (IEEE J. Solid State Circuits, 2025)

An Adaptive 56-Gb/s Duo-PAM4 Detector Using Reduced Branch Maximum Likelihood Sequence Detection in a 28-nm CMOS Wireline Receiver. - Mingche Lai; Chaolong Xu; Fangxu Lv; Jiaqing Xu; Qiang Wang 006; Yang Ou; Xiaoyue Hu; Cewen Liu; Zhouhao Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers. - Chaolong Xu; Fangxu Lv; Mingche Lai; Xingyun Qi; Qiang Wang 006; Zhang Luo; Shijie Li 002; Geng Zhang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS. - Hua Xu; Mingche Lai; Xuqiang Zheng; Zedong Wang; Jiang Xu; Sai Li; Fangxu Lv; Min Liu; Weijie Li; Zhanhao Wen; Xuan Guo; Xinhua Wang; et al. (IEEE J. Solid State Circuits, 2025)