Simulation-based hierarchical sizing and biasing of analog firm IPs. - Farakh Javid; Ramy Iskander; Marie-Minerve Louërat (BMAS, 2009)

A seamless representation for coupling transistor sizing with nanometric CMOS layout generation. - Stephanie Youssef; Farakh Javid; Damien Dupuis; Ramy Iskander; Marie-Minerve Louërat (ECCTD, 2011)

A Python-based layout-aware analog design methodology for nanometric technologies. - Stephanie Youssef; Farakh Javid; Damien Dupuis; Ramy Iskander; Marie-Minerve Louërat (IDT, 2011)

A unified platform for design and verification of mixed-signal systems based on SystemC AMS. - Yao Li 009; Ramy Iskander; Farakh Javid; Marie-Minerve Louërat (FDL, 2012)

A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS. - Yao Li 009; Ramy Iskander; Farakh Javid; Marie-Minerve Louërat (FDL (Selected Papers), 2012)

A structured DC analysis methodology for accurate verification of analog circuits. - Farakh Javid; Ramy Iskander; Marie-Minerve Louërat; François Durbin (ISCAS, 2013)

Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations. - Akram Malak; Yao Li 009; Ramy Iskander; François Durbin; Farakh Javid; Jean-Marc Guebhard; Marie-Minerve Louërat; André Tissot (Integr., 2015)